There are signs that OpenAI, the company that rose to fame with its AI models, is now eyeing the semiconductor manufacturing sector. However, can building a wafer fab be an easy success?

Recently, international media revealed details of OpenAI CEO Sam Altman’s meetings with senior executives from multiple chip manufacturers during his visit to Asia last year.

Altman visited top executives at companies such as TSMC and Samsung, proposing an ambitious plan to invest $7 trillion to build 36 new wafer fabs and data centers to drive the development of artificial intelligence. Altman envisioned that these fabs, funded by the United Arab Emirates, would produce AI chips, which OpenAI and other companies could use to build AI data centers.

The report highlighted that the scale of the investment Altman mentioned is equivalent to a quarter of the annual output of the U.S. economy. To meet OpenAI’s expansion needs for computing power, it would take several years to complete the necessary wafer fabs.

However, due to cost considerations, TSMC did not endorse Altman’s plan. TSMC executives considered Altman’s proposal too aggressive and risky. Even building a few more wafer fabs involves high risk due to the immense capital required, let alone 36 fabs.

How Much Does a Wafer Fab Cost? Hundreds of Billions of Dollars

In recent years, driven by the demand for AI models, the need for chips has surged, and wafer fabs have been expanding rapidly. However, as OpenAI’s experience shows building a wafer fab is no simple task. It faces challenges such as international dynamics, costs, and technological hurdles, with cost being the largest barrier.

The cost of a wafer fab primarily involves land and facility construction, equipment procurement, technology development and intellectual property, as well as operation and maintenance. Land and facility construction take up a significant portion, as a fab requires extensive land for building plants and basic infrastructure such as electricity, water supply, and communication.

On the equipment side, the purchase of lithography machines, etching machines, ion implanters, and thin-film deposition tools is a major expense, especially for advanced lithography machines, which are extremely costly.

Additionally, a wafer fab requires significant research and operational costs, including intellectual property, equipment maintenance, staff training, safety protocols, and environmental management, all of which demand continuous investment from manufacturers.

When all these factors are calculated, the cost of building a wafer fab is extremely high. Moreover, as chip manufacturing processes evolve, the cost of fabs continues to rise. The industry estimates that the cost of a modern fab is in the range of billions of dollars. For example, Intel’s two factories in Arizona are expected to cost $15 billion each, while Samsung’s fab in Taylor, Texas, is projected to cost $25 billion.

Regional Differences in Wafer Fab Costs

It’s also worth noting that the cost of building a wafer fab varies by region. In Asia, for example, due to a well-established supply chain, abundant talent, and policy support, the cost of building a fab is relatively lower. In regions like Europe, the U.S., and the Middle East, however, costs may be higher due to the need to import technology, train talent, and develop a complete supply chain.

(Photo credit: Intel)

To turn adversity around, Intel launched its latest AI accelerator, Gaudi 3, in late September. However, a report by the Economic Daily News indicates that the struggling giant has significantly slashed the chip’s shipment targets by over 30% for next year, which may severely impact orders for its Taiwanese supply chain.

According to the report, the move could be attributed to the Intel’s internal strategy adjustments and the fluctuation of customer demand, which prompts it to cut orders on Taiwanese companies such as TSMC, ASE Technology, and ASIC firm Alchip.

According to industrial sources cited by the report, Intel originally projected to ship 300K to 350K units of Gaudi 3 in 2025. However, the target has now been revised to 200K to 250K units, marking a reduction of more than 30%.

According to the report, after acquiring Israel-based AI chip company Habana Labs in 2019, Intel seems to be relatively conservative about their co-development of the next-gen AI accelerators. Intel’s cautious attitude is evident from its recent moves, such as expediting the conclusion of previous projects like Gaudi 2, as well as lowering the shipment target for Gaudi 3 next year.

Intel declined to comment on the matter, the report notes.

According to industrial sources cited by the report, the adjustment will pose limited impact to TSMC, which manufactures Intel’s Gaudi 3 with its 5nm node. While the demand for the foundry leader’s advanced nodes remains robust, other customers are expected to quickly fill the gap left by Intel.

In terms of IC packaging and testing services provider ASE and its subsidiary SPIL, as they also have a diversified client portfolio, with major tech companies placing orders, the capacity can be swiftly reallocated to minimize the impact, the report suggests.

Nevertheless, for those with smaller scales and a higher client concentration, the impact may be more significant. Taiwanese ASIC firm Alchip, which provides ASIC design services for Intel’s Gaudi 2 and Gaudi 3, therefore, may be more vulnerable to Intel’s potential shipment reduction, according to the report.

Unimicron, which serves as the primary supplier of substrates for Intel’s chips, may also be impacted by the fluctuation of Intel’s orders, the report notes. However, when asked about the potential impact, the company reaffirms its optimistic outlook regarding the second half of 2024, as it expects the demand for AI accelerators and optical modules to be stronger than the first half.

Currently, NVIDIA still holds the throne in the global AI chip market, with rivals such as AMD and Intel eagerly trying to catch up.

Intel’s latest effort, Gaudi 3, boasts 64 Tensor processor cores (TPCs) and eight matrix multiplication engines (MMEs) to accelerate deep neural network computations, and is specifically optimized for large-scale generative AI, according to its press release. It even claims to offer double the performance at the same cost compared to NVIDIA’s H100, the report says.

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(Photo credit: Intel)

While TSMC is making advancements on its 2nm at full throttle, an unexpected risk may be emerging, which might be more severe than most could imagine: power supply. Citing a report by S&P, a report by Wccftech highlights that compared with 2023, the foundry giant’s electricity consumption could nearly triple by 2030, accounting for about 24% of the island’s total electricity usage.

Another report by the Economic Daily News warns that the slow growth in Taiwan’s power generation may pose challenges to TSMC’s chip production, which requires high energy consumption.

Citing the data compiled by a S&P’s report titled “Power Is Increasingly A Credit Risk for TSMC,” Wccftech notes that in 2023, TSMC’s electricity consumption had reached nearly 250 GW, accounting 8% of Taiwan’s total electricity use and almost 16% of the industrial sector’s demand. However, by 2030, TSMC’s share of electricity consumption could soar significantly, contributing 23.7% of the island’s total power usage.

S&P’s calculation is based on the assumption that the TSMC’s wafer shipments will increase by 90% compared to 2023 levels, leading electricity consumption to soar to 794 GW in 2030, Wccftech notes.

It is worth noting that the S&P report, cited by Wccftech, also highlights that extreme ultraviolet (EUV) lithography systems, which are required for processes below 7nm, consume significantly more power than the older deep ultraviolet lithography systems (DUV).

The scenario would weigh heavily on semiconductor heavyweights as they are eagerly pursuing for more advanced nodes. TSMC’s move to 3nm chip production is fueling S&P’s projections of the company’s skyrocketing electricity consumption, Wccftech says.

To put things in context, the report also cites data from Taiwan’s state-owned electricity provider, TaiPower, to show that the island’s electricity reserve margin continues to fall short of the government’s 15% target. While the household electricity consumption continues to decline, TSMC’s power needs, in contrast, keeps growing.

Moreover, according to the Economic Daily News, which also cites S&P’s report, when the electricity reserve margin drops below 10%, the stability of the power supply can be affected.

Citing S&P’s report, the Economic Daily News states that the growth of Taiwan’s power supply is relatively limited. In addition, Taiwan’s policy of replacing cheaper coal and nuclear energy with natural gas and renewable energy will put more pressure on future electricity prices, which may also influence the stability of power supply.

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• [News] TSMC Took Another Step in Advanced Process Expansion

(Photo credit: TSMC)

As TSMC has reportedly begun trial production of 2nm chips in its Baoshan Plant in Hsinchu, northern Taiwan, the schedule of mass producing 2nm in 2025 remains on track. A report by Commercial Times reveals that the price of 2nm wafers is expected to double compared to 4/5nm, which may exceed USD 30,000 per wafer.

While the yield rates for advanced nodes of Intel and Samsung are rumored to be relatively low, the rising price of 2nm wafers reflects TSMC’s market monopoly as well as its strong pricing power, the report notes.

Citing comments by sources from semiconductor companies, the report states that fabs have invested heavily in advanced processes. For instance, the R&D investment of 3nm may exceed USD 4 billion, with key partners in TSMC’s supply chain, such as Taiwanese IP providers and material suppliers, playing a critical role.

On the other hand, executives from IC design houses cited by the report reveal that even from the perspective of IC design, the R&D cost for advanced nodes remains high. For instance, the development cost for 28nm is approximately USD 50 million, while 16nm may require an investment of USD 100 million. For 5nm, the R&D cost has soared to USD 550 million, if the expenditure on IP licensing, software verification, and design architecture are factored in.

According to the report, foundries have invested even more, with research institutions estimating that R&D expenses for 3nm may range from USD 4 billion to USD 5 billion. Additionally, constructing a 3nm fab is expected to cost at least USD 15 billion to USD 20 billion. All these factors may lead to the high pricing of wafers in the advanced nodes.

Therefore, for a foundry, the development of a new-generation of node involves massive efforts, and needed to be supported by partners in three key sectors: equipment, software (including IP and EDA tools), and materials, the report notes. Once their products have been validated by the foundry, suppliers can usually secure long-term partnership.

With 2nm set to debut in 2025, TSMC’s key suppliers are expected to see explosive profit growth, the report indicates. According to the report, Taiwanese IP firm M31, for example, has already developed IP that supports the 2nm platform for both smartphones and high-performance computing. Likewise, eMemory has disclosed that it is collaborating with leading foundries to develop 2nm.

On the other hand, as 2nm processes require thinner wafers, Taiwan-based materials companies, such as Kinik and Phoenix Silicon International Corp., have entered the markets of diamond discs and reclaimed wafers.

According to the report, in terms of reclaimed wafers, the market value for 2nm is approximately 4.6 times that of 28nm. In addition, the number of dummy wafers will also increase in advanced processes, which benefit suppliers with more volume and higher average prices.

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(Photo credit: TSMC)

The competition between Samsung and TSMC has intensified not only in securing international IC design clients but also in the field of South Korean IC design companies. According to a report by ZDNet Korea, major South Korean AI semiconductor fabless companies, which previously used Samsung’s foundry facilities, are now diversifying their manufacturing by using TSMC’s fabs for new chip mass production.

Industry sources cited by ZDNet Korea reveal that FuriosaAI initially used Samsung’s 14nm process for its first-generation chip, “Warboy,” but switched to TSMC’s 5nm process for its second-generation chip, “Renegade.” Notably, Renegade became the first chip in South Korea’s AI semiconductor sector to utilize 2.5D packaging technology with CoWoS and HBM3 memory. FuriosaAI is also planning to use TSMC’s 5nm process for its next-generation chip, “RenegadeS,” set to launch in the fourth quarter.

Similarly, DeepX, after using Samsung’s foundry process, adopted TSMC’s technology for its latest chip development this year. The company’s “DX-V3” system-on-chip (SoC) is being developed using TSMC’s 12nm process, with a target to release samples later this year. DeepX’s earlier chips, the “DX-M1” AI accelerator and “DX-H1” AI server accelerator, were produced using Samsung’s 5nm process, while the “DX-V1” AI SoC solution was made with Samsung’s 28nm process. The “DX-M1” entered mass production last month. ZDNet Korea also reports that DeepX is currently discussing with Samsung the development of next-generation chips using processes more advanced than 5nm.

Another South Korean IC design company, Moblinet, is utilizing both Samsung and TSMC’s foundry services. Its first-generation chip, “Eris,” was manufactured using Samsung’s 14nm process and began mass production in March this year. The second-generation chip, “Regulus,” is being produced using TSMC’s 12nm process and is expected to launch next year after completing testing.

ZDNet Korea also cites industry experts who emphasize that Samsung’s foundry services need to not only focus on attracting large clients but also improve services for smaller fabless companies. Similar to how TSMC grew by nurturing partnerships with small fabless firms, Samsung should bolster its process technology and develop an ecosystem for IP and fabless companies.

According to TrendForce data, TSMC maintained a global foundry market share of 62.3% in the second quarter of this year, while Samsung held an 11.5% share.

Meanwhile, in the race for major international client orders, WCCFTECH reports that Qualcomm is pursuing a dual-sourcing strategy for its Snapdragon 8 Gen 5 chip, partnering with both TSMC and Samsung. Qualcomm has previously attempted this approach, but Samsung’s inconsistent yields thwarted the plan. Qualcomm is now reportedly considering TSMC’s 3nm ‘N3P’ technology for the high-performance variant of the Snapdragon 8 Gen 5, while Samsung’s SF2, also known as 2nm GAA, is expected to be used for a lower-end version.

(Photo credit: TSMC)