According to a report from Taiwan’s TechNews, as we approach the fourth quarter, which marks the peak period for negotiations between the semiconductor manufacturing leader TSMC and its suppliers, the supply chain is indicating that TSMC is expected to follow a similar approach to that of 2022. This means that in anticipation of an unclear overall semiconductor market outlook for 2024, TSMC is likely to either slightly reduce prices or refrain from implementing price cuts when dealing with its suppliers.

Suppliers have noted that in 2022, TSMC generally adopted a strategy of minor price reductions or no price cuts during negotiations. This approach helped alleviate the pressure on suppliers facing inflation and rising raw material costs. However, for 2024, with the semiconductor industry’s overall recovery still uncertain, and procurement volumes not expected to increase significantly, it is anticipated that TSMC will maintain a similar stance with its suppliers as it did in 2022.

Considering the current state of the semiconductor industry, market analysts anticipate that TSMC’s revenue growth in the fourth quarter could reach between 7% and 9%. This growth is primarily attributed to the upcoming release of Apple’s iPhone 15 series in September, with shipment volumes expected to reach 86 million units. Additionally, the surge in market demand for data center chips from NVIDIA is contributing to TSMC’s robust performance. It’s projected that TSMC’s third-quarter revenue will be in the range of $16.5 billion to $17.5 billion, and the fourth quarter is expected to witness further growth, reaching $18.6 billion, representing an average quarterly growth of 8%.

However, despite the optimistic outlook for the fourth quarter, the prospects for 2024 may differ. This uncertainty stems from efforts by U.S. consumers and businesses to cope with high inflation, questions about potential interest rate hikes, and the looming possibility of an economic downturn. Additionally, China’s economic performance has been lackluster, and these two markets constitute a significant portion of TSMC’s revenue. This combination of factors results in a high level of uncertainty, which is expected to influence TSMC’s procurement strategies and bargaining power with suppliers in a more cautious manner, given the prevailing uncertain conditions.

(Photo credit: TSMC)

TSMC’s CoWoS advanced packaging capacity shortage is causing limitations in NVIDIA’s AI chip output. Reports are emerging that NVIDIA is willing to pay a premium for alternative manufacturing capacity outside of TSMC, setting off a surge in massive overflow orders. UMC, the supplier of interposer materials for CoWoS, has reportedly raised prices for super hot runs and initiated plans to double its production capacity to meet client demand. ASE, an advanced packaging provider, is also seeing movement in its pricing.

In response to this, both UMC and ASE declined to comment on pricing and market rumors. In addressing the CoWoS advanced packaging capacity issue, NVIDIA previously confirmed during its financial report conference that it had certified other CoWoS packaging suppliers for capacity support and would collaborate with them to increase production, with industry speculation pointing towards ASE and other professional packaging factories.

TSMC’s CEO, C.C. Wei, openly stated that their advanced packaging capacity is at full utilization, and as the company actively expands its capacity, they will also outsource to professional packaging and testing factories.

It’s understood that the overflow effect from the inadequate CoWoS advanced packaging capacity at TSMC is gradually spreading. As the semiconductor industry as a whole adjusts its inventory, advanced packaging has become a market favorite.

Industry insiders point out that the interposer, acting as a communication medium within small chips, is a critical material in advanced packaging. With a broad uptick in demand for advanced packaging, the market for interposer materials is growing in parallel. Faced with high demand and limited supply, UMC has raised prices for super-hot-run interposer components.

UMC revealed that it has a comprehensive solution in the interposer field, including carriers, customed ASICs, and memory, with cooperation from multiple factories forming a substantial advantage. If other competitors are entering this space now, they might not have the quick responsiveness or abundant peripheral resources that UMC does.

UMC emphasized that compared to competitors, its competitive advantage in the interposer field lies in its open architecture. Currently, UMC’s interposer production primarily takes place in its Singapore plant, with a current capacity of about 3,000 units, with a target of doubling to six or seven thousand to meet customer demand.

Industry analysts attribute TSMC’s tight CoWoS advanced packaging capacity to a sudden surge in NVIDIA’s orders. TSMC’s CoWoS packaging had primarily catered to long-term partners, with production schedules already set, making it unable to provide NVIDIA with additional capacity. Moreover, even with tight capacity, TSMC won’t arbitrarily raise prices, as it would disrupt existing client production schedules. Therefore, NVIDIA’s move to secure additional capacity support through a premium likely involves temporary outsourced partners.

(Photo credit: NVIDIA)

According to a report by Taiwan’s Commercial Times, Goldman Sachs Securities has noted that Intel has been consistently grappling with process upgrade delays since the 10-nanometer fabrication process. Recently, the company has decided to establish a foundry-like relationship between its manufacturing groups and
internal product business units. With the market scale growing increasingly substantial, it is anticipated that Intel will expand its outsourcing to TSMC in 2024 and 2025. In the rising trend of outsourced manufacturing, TSMC stands as the major beneficiary.

Goldman Sachs’ analysis reveals that the total addressable market of Intel’s outsourcing orders for 2024 and 2025 is set at $18.6 billion and $19.4 billion, respectively. During the same period, the total addressable market scope for TSMC’s wafer fabrication services amounts to $5.6 billion and $9.7 billion, approximately accounting for 6.4% and 9.4% of TSMC’s overall revenue in the corresponding years.

Prominent semiconductor industry analyst Andrew Lu also explains that Intel’s wafer chip manufacturing division competes with TSMC, rather than its design division. The design division is striving for survival in the high-speed computing semiconductor sector, and it is currently hopeful for close collaboration with TSMC. Lu even predicts that Intel’s wafer manufacturing and design divisions will inevitably be further separated into two companies several years down the line.

Semiconductor process technology is nearing the boundaries of known physics. In order to continually enhance processor performance, the integration of small chips (chiplets) and heterogeneous Integration has become a prevailing trend. It is also regarded as a primary solution for extending Moore’s Law. Major industry players such as TSMC, Intel, Samsung, and others are vigorously developing these related technologies.

What are SoC, SiP, and Chiplet?

To understand Chiplet technology, we must first clarify two commonly used terms: SoC and SiP. SoC (System on Chip) involves redesigning multiple different chips to utilize the same manufacturing process and integrating them onto a single chip. On the other hand, SiP (System in Package) connects multiple chips with different manufacturing processes using heterogeneous integration techniques and integrates them within a single packaging form.

Chiplet technology employs advanced packaging techniques to create a SiP composed of multiple small chips. It integrates small chips with different functions onto a single substrate through advanced packaging techniques. While Chiplets and SiPs may seem similar, Chiplets are essentially chips themselves, whereas SiP refers to the packaging form. They have differences in functionality and purpose.

Chiplets: Today’s Semiconductor Development Trend

The design concept of Chiplet technology offers several advantages over SoC, notably in significantly improving chip manufacturing yield. As chip sizes increase to enhance performance, chip yield decreases due to the larger surface area. Chiplet technology can integrate various smaller chips with relatively high manufacturing yields, thus enhancing chip performance and yield.

Furthermore, Chiplet technology contributes to reduced design complexity and costs. Through heterogeneous integration, Chiplets can combine various types of small chips, reducing integration challenges in the initial design phase and facilitating design and testing. Additionally, since different Chiplets can be independently optimized, the final integrated product often achieves better overall performance.

Chiplets have the potential to lower wafer manufacturing costs. Apart from CPUs and GPUs, other units within chips can perform well without relying on advanced processes. Chiplets enable different functional small chips to use the most suitable manufacturing process, contributing to cost reduction.

With the evolution of semiconductor processes, chip design has become more challenging and complex, leading to rising design costs. In this context, Chiplet technology, which simplifies design and manufacturing processes, effectively enhances chip performance, and extends Moore’s Law, holds significant promise.

Applications and Development of Chiplets

In recent years, global semiconductor giants like AMD, TSMC, Intel, NVIDIA, and others have recognized the market potential in this field, intensively investing in Chiplet technology. For example, AMD’s recent products have benefited from the ‘SiP + Chiplet’ manufacturing approach. Moreover, Apple’s M1 Ultra chip achieved high performance through a customed UltraFusion packaging architecture. In academia, institutions like the University of California, Georgia Tech, and European research organizations have begun researching interconnect interfaces, packaging, and applications related to Chiplet technology.

In conclusion, due to Chiplet technology’s ability to lower design costs, reduce development time, enhance design flexibility and yield, while expanding chip functionality, it is an indispensable solution in the ongoing development of high-performance chips.

This article is from TechNews, a collaborative media partner of TrendForce.

According to Taiwan’s TechNews report, Intel has revealed the architecture and supply schedule of the new generation data center Xeon processors, Sierra Forest and Granite Rapids. They are also set to unveil the consumer processor codenamed Meteor Lake in mid-September. However, with the semiconductor market’s current weak recovery, the impact of Intel’s new processors on driving upgrades and benefiting Taiwanese supply chain manufacturers remains uncertain, making it a market focal point.

Regarding the consumer-oriented Meteor Lake processor, industry sources suggest that it will not only be the first to adopt “Intel 4” technology, but also the first to utilize EUV lithography for cost reduction in mass-producing CPU tiles. TSMC will assist in production using the 5/6 nanometer process for graphics chip modules (GFX tile), system chip modules (SoC tile), and input/output chip modules (IOE tile), aiming for higher yields to decrease production costs.

Furthermore, the Meteor Lake processor shifts from traditional monolithic chip design to chiplet technology. After separating functions like graphics, system, and I/O chips, it employs the 3D Foveros advanced packaging technology. Through Foveros interconnects, multiple chiplets are vertically stacked into one chip. This approach not only increases the yield of critical modules but also reduces costs, granting Intel greater flexibility in rapidly creating next-generation chip capacities.

For the upcoming Meteor Lake processor, its direct beneficiary is undoubtedly TSMC, which assists in producing graphics chip modules, system chip modules, and input/output chip modules using the 5/6 nanometer process. This collaboration not only boosts revenue but also maintains the ongoing partnership with Intel.

However, despite Taiwanese foundries and board manufacturers securing orders for Intel’s new-generation processors, the current economic environment remains unfavorable. With a cautious and conservative outlook on consumer spending in the global market, the launch of Intel’s new products could either boost supply chain revenue or lead to increased inventory in the next phase, requiring further observation.

(Photo credit: Intel)