In response to the demands of high-performance computing, AI, 5G, and other applications, the shift towards chiplet and the incorporation of HBM memory has become inevitable for advanced chips. As a result, packaging has transitioned from 2D to 2.5D and 3D formats.

With chip manufacturing advancing towards more advanced process nodes, the model of directly packaging chips using advanced packaging technology from wafer foundries has emerged. However, this approach also signifies that wafer foundries will encroach upon certain aspects of traditional assembly and testing, leading to ongoing discussions about the ‘threat’ to traditional assembly and test firms since TSMC’s entry into advanced packaging in 2011.

But is this perspective accurate?

In fact, traditional assembly and test firms remain competitively positioned. Firstly, numerous electronic products still rely on their diverse traditional packaging techniques. Particularly, with the rapid growth of AIoT, electric vehicles, and drones, the required electronic components often still adopt traditional packaging methods. Secondly, faced with wafer foundries actively entering the advanced packaging domain, traditional assembly and test firms have not been idle, presenting concrete solutions to the challenge.

Advanced Packaging Innovations by Traditional Assembly and Test Firms

Since 2023, AI and AI server trends have rapidly emerged, driving the demand for AI chips. TSMC’s 2.5D advanced packaging technology, known as CoWoS, has played a pivotal role. However, the sudden surge in demand stretched TSMC’s capacity. In response, major traditional assembly and test firms such as ASE and Amkor have demonstrated their technical prowess and have no intention of being absent from this field.

For instance, ASE’s FOCoS technology enables the integration of HBM and ASIC. It restructures multiple chips into a fan-out module, which is then placed on the substrate, achieving the integration of multiple chips. Their FOCoS-Bridge technology, unveiled in May this year, utilizes silicon bridges (Si Bridge) to accomplish 2.5D packaging, bolstering the creation of advanced chips required for applications like AI, data centers, and servers.

Additionally, SPIL, a subsidiary of ASE, offers the FO-EB technology, a powerful integration of logic IC and HBM. As depicted below, this technology eschews silicon interposers, utilizing silicon bridges and redistribution layers (RDL) for connections, similarly capable of 2.5D packaging.

Another major player, Amkor, has not only collaborated with Samsung to develop the H-Cube advanced packaging solution but has also long been involved in ‘CoWoS-like technology.’ Through intermediary layers and through-silicon via (TSV) technology, Amkor can interconnect different chips, also possessing 2.5D advanced packaging capabilities.

China’s major assembly and test firm, Jiangsu Changjiang Electronics Technology (JCET), employs the XDFOI technology, integrating logic ICs with HBM through TSV, RDL, and microbump techniques, aimed at high-performance computing.

Given the recent surge in demand for high-end GPU chips, TSMC’s CoWoS capacity has fallen short, and NVIDIA is actively seeking support from second or even third suppliers. The ASE Group and Amkor have secured partial orders through their packaging technologies. This clearly illustrates that traditional assembly and test firms, even when faced with the entry of wafer foundries into the advanced packaging domain, still possess the capability to compete.

In terms of product types, wafer foundries focus on advanced packaging technology for major players like NVIDIA and AMD. Meanwhile, other products not in the highest-end category still opt for traditional assembly and test firms like ASE, Amkor, and JCET for manufacturing. Overall, with their presence in advanced packaging, as well as a hold on the expanding existing packaging market, traditional assembly and test firms continue to maintain their market competitiveness.

(Photo credit: Amkor)

According to Taiwan’s Commercial Times, TSMC continues to face challenges from ongoing price undercutting and competitive bidding in mature semiconductor manufacturing processes. Concerns arise about the company’s ability to offset these challenges with AI-related orders. Reports from the market suggest that on July 20th, TSMC revised down its fiscal forecast for the year for the second time, slashing its annual revenue target (in USD) from an anticipated decline of 1% to 6% to a significant reduction of 10%. However, given the persistent sluggish economic conditions of late, there is speculation of a potential third adjustment that could lead to a year-on-year revenue decline of 12%.

In the current investment landscape, artificial intelligence has become a focal point this year. Additionally, the strong demand for CoWoS packaging has contributed to a positive outlook for TSMC. However, it’s important to note that AI’s contribution to TSMC’s overall revenue is not substantial.

Using the popular H100 model from NVIDIA as an example, it only impacts TSMC’s performance in the N4 manufacturing process. This limited contribution falls short of countering the downward trend in consumer product demand utilizing the N3 and N7 manufacturing processes.

Market Speculations Emerge About TSMC’s Performance and Challenges

Market sources indicate that TSMC’s performance in mature processes (7nm and above) accounted for 47% of its output in the second quarter. While prices managed to hold steady in the first half of the year, ongoing softness in end-user demand has prompted Chinese manufacturers to engage in aggressive expansion, price reduction, and competition for orders, which inevitably impacts TSMC. There are even reports circulating about a potential loosening of 7nm production capacity.

In response, TSMC stated that its perspective and outlook on market demand align with the contents of its July press conference. As of now, no new updates are available. Furthermore, TSMC refrains from commenting on market speculations or shifts in customer business dynamics.

(Photo credit: TSMC)

In recent market speculations, TSMC is rumored to have reduced its 8-inch wafer manufacturing quotes by as much as 30%, with subsequent reports suggesting that South Korean wafer foundries are following suit in lowering 8-inch wafer production prices.

According to TrendForce’s channel check, TSMC’s current strategy for 8-inch processes involves bundling spot deal negotiations with one-time pricing or offering discounts and rebates on initial NRE fees, without implementing an across-the-board price cut.

However, observations from the order books indicate a genuine decline in demand for 8-inch products. Presently, customers have started revising their orders through the first quarter of 2024. The possibility of TSMC reducing prices for 8-inch wafers cannot be ruled out.

Similarly, the industry has also seen reports of South Korean wafer foundries Samsung and Dongbu HiTek considering price reductions for their 8-inch wafer plants. TrendForce indicates that the price adjustments in South Korea’s 8-inch wafer foundries follow a similar pattern of spot deal reductions, primarily centered around one-time negotiations. Customers with long-term agreement already have lower prices, without any instances of price reduction.

Both 12-inch and 8-inch wafer fabrication utilization rates have shown less-than-expected recovery, leading TrendForce to estimate a year-on-year decrease of around 13% in the overall semiconductor foundry revenue for 2023.

(Photo credit: TSMC)

According to a report by Taiwan’s Commercial Times, global smartphone brands are set to introduce a series of flagship-level new products. Following the introduction of Apple’s A17 chip using TSMC’s 3-nanometer process, Qualcomm’s next-generation processor Snapdragon 8 Gen 3 and MediaTek’s Dimensity 9300 are expected to be unveiled in October. These chips will be manufactured using TSMC’s N4P process, with plans to further transition to the N3E process next year.

Industry source have indicated that TSMC’s 3-nanometer yield is gradually improving, coupled with the return of N4P orders, providing a counterbalance against the impact of sluggish end market demand.

Commercial Times’ report highlights that TSMC previously expressed strong demand for its N3 process, projecting substantial growth in the second half of the year. The N3 process will support high-performance computing (HPC) and smartphone platforms, with an anticipated contribution of 4-6% to the company’s revenue in 2023. Additionally, N3E has already been verified and received its first batch of customer product design approvals, with mass production expected to commence in the fourth quarter. TSMC aims to achieve a monthly production capacity of 100,000 wafers in its 3-nanometer process by the end of the year to cater to Apple’s demands.

According to Bloomberg’s recent exposure of Apple’s projected M3 processor product roadmap set for release this fall, the basic M3 processor consists of 4 high-performance and 4 energy-efficient cores, paired with 10 GPU cores. M3 Pro comes in two versions: a basic version equipped with 12 cores (6 high-performance and 6 energy-efficient) and 18 GPU cores, and a higher-tier version with 14 CPU cores and 20 GPU cores.

M3 Max also offers two versions, featuring a fully-equipped 16-core CPU. The main difference between the basic and higher-tier versions lies in the GPU cores—32 for the former and a whopping 40 for the latter. The most powerful variant, M3 Ultra, essentially doubles the configuration of M3 Max, boasting 32 CPU cores paired with either 64 or 80 GPU cores. Industry experts widely regard TSMC as the primary beneficiary of these developments.

(Photo credit: TSMC)

According to a report by Taiwan’s Commercial Times, JPMorgan’s latest analysis reveals that AI demand will remain robust in the second half of the year. Encouragingly, TSMC’s CoWoS capacity expansion progress is set to exceed expectations, with production capacity projected to reach 28,000 to 30,000 wafers per month by the end of next year.

The trajectory of CoWoS capacity expansion is anticipated to accelerate notably in the latter half of 2024. This trend isn’t limited to TSMC alone; other players outside the TSMC are also actively expanding their CoWoS-like production capabilities to meet the soaring demands of AI applications.

Gokul Hariharan, Head of Research for JPMorgan Taiwan, highlighted that industry surveys indicate strong and unabated AI demand in the latter half of the year. Shortages amounting to 20% to 30% are observed with CoWoS capacity being a key bottleneck and high-bandwidth memory (HBM) also facing supply shortages.

JPMorgan’s estimates indicate that Nvidia will account for 60% of the overall CoWoS demand in 2023. TSMC is expected to produce around 1.8 to 1.9 million sets of H100 chips, followed by significant demand from Broadcom, AWS’ Inferentia chips, and Xilinx. Looking ahead to 2024, TSMC’s continuous capacity expansion is projected to supply Nvidia with approximately 4.1 to 4.2 million sets of H100 chips.

Apart from TSMC’s proactive expansion of CoWoS capacity, Hariharan predicts that other assembly and test facilities are also accelerating their expansion of CoWoS-like capacities.

For instance, UMC is preparing to have a monthly capacity of 5,000 to 6,000 wafers for the interposer layer by the latter half of 2024. Amkor is expected to provide a certain capacity for chip-on-wafer stacking technology, and ASE Group will offer chip-on-substrate bonding capacity. However, these additional capacities might face challenges in ramping up production for the latest products like H100, potentially focusing more on older-generation products like A100 and A800.

(Photo credit: TSMC)