According to a report from Taiwan’s Economic Daily, the construction of TSMC’s 2-nanometer fab in the Central Taiwan Science Park (CSTP) is confirmed to be delayed until next year due to land acquisition and construction timelines.

The Taiwan Central Science Park Administration indicated that this project has been delayed by a year and a half, and the operational schedule is now too tight. After receiving approval from the Taichung City government, it still needs to undergo review by the Construction and Planning Agency Ministry of the Interior. It is anticipated that the urban planning announcement by the Taichung City government will be made by the end of the year, a prerequisite for initiating land acquisition procedures. However, meeting this year’s end deadline for land acquisition is now deemed unfeasible.

The Central Science Park Administration was notified by the Taichung City government today that the expansion project for Phase 2 of the CSTP, crucial for TSMC’s 2-nanometer fab, has been scheduled for urban planning review on the 25th of this month.

Due to repeated delays in the urban planning approval process for the CSTP Phase 2 expansion, TSMC recently made the decision to plan for the construction of a 2-nanometer fab in Kaohsiung.

It’s worth noting that the inclusion of the CSTP Phase 2 expansion project in this month’s urban planning review hinges on TSMC’s announcement of its 2-nanometer fab plans in Kaohsiung. The breakthrough came after Taiwan Power Company and Taiwan Water Corporation finally issued assurances that TSMC’s CSTP 2-nanometer fab’s development and operation would not compromise the assurance of power and water supply for Taichung residents, which provided a turning point for the project.

(Photo credit: TSMC)

According to the news from Mydrivers.com, TSMC announced its ambitious plans for constructing cutting-edge 4nm and 3nm chip fabs in the United States. The move is expected to generate tens of thousands of job opportunities in the US job market. However, TSMC’s timeline for commencing production at its inaugural 4nm fab has been pushed back from 2024 to 2025. The attributed cause behind this delay is the insufficient availability of skilled American workers, causing setbacks in equipment installation.

This situation has led to a heated dispute between TSMC and local labor unions. TSMC’s assertion of a skilled worker deficit in the US has sparked disagreement from the unions. They assert that TSMC’s stance is a pretext for bringing in lower-wage overseas labor to vie for domestic employment opportunities. TSMC, on the other hand, refutes these claims, emphasizing that employing local staff on assignment doesn’t undermine their US-based operations or recruitment efforts.

Apart from the skill-related quandary, the delay in TSMC’s factory plans may have an underlying factor – the scorching conditions in Phoenix, Arizona. Sources report that the city has experienced an unbroken streak of over 20 days with temperatures hovering around 43 degrees Celsius. Notably, this heat wave has raised internal questioning within TSMC about the wisdom of selecting a desert-adjacent location for their facility.

According to this industry insider, the intense heat seemingly played a role in impeding progress. The sweltering climate of over 40 degrees Celsius undoubtedly hampers worker productivity, particularly for outdoor tasks.

The informer indicated that TSMC had an alternative option when choosing a location for its US facility. Aside from Arizona, they could have set up shop in Portland, the capital of Oregon, which is also a hub for the semiconductor industry. However, TSMC’s rationale for settling in Arizona remains undisclosed.

Notably, Phoenix, Arizona, is also a focal point for Intel’s chip investments, with the company injecting 20 billion USD into the establishment of new wafer fabs over the past couple of years.

(Source: https://news.mydrivers.com/1/928/928753.htm)

According to the news from Money UDN, amid a tough semiconductor market, once-stable long-term contracts for silicon wafer makers have turned uncertain. A major Taiwanese foundry seeks price cuts in upcoming contracts from a Japanese supplier. Intense negotiations are ongoing, potentially affecting industry dynamics and pricing strategies due to the Japanese suppliers’ pivotal role in the supply chain.

Market insiders suggest silicon wafer makers may resist price reductions due to their vital role in foundries. Reports hint at foundries’ challenges and the ripple effects on critical materials suppliers.

Globally, Japan’s Shin-Etsu and SUMCO are top silicon wafer suppliers, trailed by Taiwan’s GlobalWafers, Germany’s Siltronic, and South Korea’s SK Siltron. And Taiwan SUMCO joint venture with Formosa Plastics Group as “Formosa Sumco Technology”, and other companies like Wafer Works. With over 30% market share, Shin-Etsu leads, closely followed by SUMCO, combining for around 55% to 60% global share.

Taiwan’s foundries include TSMC, UMC, VIS, and PSMC, among others. TSMC, with a global market share exceeding 50%, holds a leading position in the industry.

Silicon wafers are essential raw materials for semiconductor foundries, integrated device manufacturers (IDMs), and memory manufacturers. Presently, the standard duration for silicon wafer long-term contracts ranges from three to 8 years, specifying annual supply and demand quantities. In the previous semiconductor boom, these long-term contracts often featured escalating prices year by year.

Semiconductor market shifts led to reduced foundry capacity use, heightening tensions with silicon wafer makers’ clients. Delays emerged in the last quarter, leading to agreements between manufacturers and clients. This trend has persisted into the first half of this year. Silicon wafer industry insiders acknowledge slow end-market demand recovery and relatively high client inventories.

Amidst this situation of overflowing inventories, reports indicate that a major Taiwanese silicon wafer foundry is requesting Japanese silicon wafer suppliers to not only agree to further delays in this year’s contracted shipments but also to lower prices for next year. However, no formal agreement has been reached by the silicon wafer manufacturers at this stage.

A juridical person suggests that the negotiations are currently at a deadlock, and the situation might become clearer in the fourth quarter. If the silicon wafer manufacturers eventually concede, they are unlikely to publicly admit it, in order to prevent other clients from seeking similar adjustments and causing wider disruptions.

Market insiders also reveal that the Japanese silicon wafer manufacturers facing price reduction demands are currently operating relatively well and are adopting a firm stance. From the perspective of the foundries, they are hoping for support from their supply chain partners to alleviate the pressure. Normal silicon wafer inventories typically span two to three months, yet certain silicon wafer foundries are already grappling with high inventory levels, particularly for 8-inch wafers, which might persist throughout this year.

(Source: https://money.udn.com/money/story/5612/7366962)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC

According to a report by Taiwan Economic Daily, industry sources have revealed that due to sluggish terminal demand and market competition, TSMC and Vanguard have recently been progressively lowering their prices for 8-inch wafer foundry services, with reductions as high as 30%.

While 8-inch wafer foundry services do not constitute a major portion of TSMC’s revenue, the company has historically maintained a relatively steadfast pricing strategy, refraining from frequent price hikes or reductions. The current reduction of up to 30% has raised significant attention.

The report states that the semiconductor industry is experiencing a downturn in prosperity, resulting in decreased capacity utilization at wafer foundries. Within this context, demand for 8-inch wafers is weaker compared to 12-inch wafers, leading some manufacturers to see their 8-inch wafer utilization rates drop to around 60%.

Regarding the price reduction, analysts at Nomura Securities suggest that this move is primarily aimed at countering Texas Instruments (TI), a global leader in analog ICs, which has significantly lowered prices for products such as power management ICs, triggering a worldwide semiconductor price war that has impacted related industries. In response, IC design companies are hoping for price reductions from foundries such as TSMC and to lower costs and compete against TI.

IC design firms have indicated that they have not received any official notification of price reductions for 8-inch wafer foundry services. They emphasized that TSMC has never implemented such a substantial reduction of up to 30% since its establishment, raising doubts about the authenticity of the news. TSMC has declined to comment on pricing matters.

(Photo credit: TSMC)