NVIDIA’s robust financial report reveals the true impact of AI on the technology industry, particularly in the AI server supply chain. …

Apple’s latest MR device, the “Vision Pro,” utilizes Micro OLED technology. This technology, along with Micro LED, is considered the next generation of display technology. So what are the differences between Micro OLED and Micro LED, and which one is better suited for AR/VR/MR devices?

According to market research firm TrendForce, ideal smart glasses must meet three major criteria. Firstly, to minimize the burden of wearing glasses, the display engine’s size should be below 1 inch. Secondly, in terms of content recognition requirements, the display brightness specification should reach at least 4,000 nits to ensure immunity to external factors such as weather or venue conditions. Lastly, the resolution should be at least 3,000 PPI to ensure clear projection and magnification.

Currently, Micro LED and Micro OLED are the primary technologies that meet these requirements. However, Micro LED is still in the early stages of AR technology development and faces several challenges that need to be overcome. Therefore, Micro OLED is currently the mainstream technology in the field.

Micro OLED technology enables full-color capabilities and has become the preferred choice for AR/VR manufacturers. According to TrendForce’s comparison of display engines, Micro LED outperforms Micro OLED in pixel size, luminous efficiency, and brightness. It appears to be the most suitable for AR glasses based on specifications. However, Micro LED is currently limited to a single green color, while Micro OLED can achieve full color. As a result, Micro OLED has a competitive advantage in AR/VR devices.

In terms of manufacturers, Sony remains the main supplier for Micro OLED technology. Due to their longer investment time and technological advantages, South Korean manufacturers Samsung and LG Display (LGD) are expected to join Apple’s MR supply chain in 2024.

Last year, reports suggested that Samsung initially considered Micro OLED a niche market and lagged behind its competitor, LGD. However, due to demands from Apple, Meta, and Samsung’s parent company, they began developing Micro OLED in the third quarter of last year. The latest news reveals that Samsung will acquire American Micro OLED display manufacturer eMagin for a price of $218 million.

Meanwhile, Meta will also collaborate with South Korean semiconductor giants SK hynix and LGD to develop Micro OLED panels for Meta XR (Extended Reality) devices. This partnership is expected to lead to more Micro OLED applications in AR/VR in the future.

Micro LED technology is still facing bottlenecks, but it has the potential to surpass Micro OLED in the medium to long term. TrendForce states that Micro LED AR glasses, due to the bottleneck in achieving full colorization, primarily display monochromatic information such as informational prompts, navigation, translation, and note-taking functions. Achieving higher resolutions requires chip miniaturization, reducing the size of Micro LED to 5 micrometers. In this situation, epitaxial processes are affected by wavelength uniformity issues, which impact yield. Additionally, smaller chips raise concerns about the external quantum efficiency (EQE) of red chips.

Overall, although Micro LED faces many challenges in AR glasses, it still outperforms Micro OLED in contrast, responsiveness, lifespan, power consumption, and other specifications. Considering the limitations of waveguide component technology in transparent AR glasses, which restricts optical efficiency from exceeding 1%, Micro LED remains an excellent choice in the medium to long term.

Therefore, if Apple wants to introduce Micro LED technology, it plans to start with the Apple Watch. However, the project’s launch has been delayed from 2024 to a later date, possibly beyond 2025, due to technological bottlenecks. In fact, over the past decade, Apple has invested significant funds in collaboration with ams Osram to develop Micro LED components. Once the technology is ready for mass production, Apple is likely to take charge of the critical “mass transfer” process, which may be carried out at its secret research and development center in Longtan, Taoyuan.

It’s worth noting that in addition to Micro LED, the Longtan research and development center is also where Apple collaborates with TSMC on Micro OLED technology for MR devices.

(Photo credit: Apple)

Semiconductor manufacturing leader TSMC held its annual shareholder meeting on June 6, addressing issues including advanced process development, revenue, and capital expenditure. TSMC’s Chairman Mark Liu and President C.C. Wei answered a series of questions. The key points from the industry are summarized as follows:

2023 Capital Expenditure Leaning towards $32 Billion

For TSMC’s Q2 and full-year outlook for this year, the consolidated revenue forecast is between $15.2 and $16 billion, a decrease of 5%-10% from the first quarter. Gross profit margin is expected to range between 52%-54%, and operating profit margin between 39.5%-41.5%. Chairman Mark Liu revealed that this year’s capital expenditure is expected to lean more towards $32 billion.

TSMC’s President C.C. Wei lowered the 2023 growth forecast for the overall semiconductor market (excluding memory), expecting a mid-single digit percentage decrease. The revenue in the wafer manufacturing industry is expected to decrease by a high single digit percentage. At this stage, the overall revenue for 2023 is expected to decrease by a low-to-mid single digit percentage, sliding approximately 1%-6%.

Advanced Process N4P to be Mass Produced this Year

TSMC’s total R&D expenditure for 2022 reached $5.47 billion, which expanded its technical lead and differentiation. The 5-nanometer technology family entered its third year of mass production, contributing 26% to the revenue. The N4 process began mass production in 2022, with plans to introduce the N4P and N4X processes. The N4P process technology R&D is progressing smoothly and is expected to be mass-produced this year. The company’s first high-performance computing (HPC) technology, N4X, will finalize product design for customers this year.

Advanced Packaging Demand Far Exceeds Capacity

Due to the generative AI trend initiated by ChatGPT, the demand for advanced packaging orders for TSMC has increased, forcing an increase in advanced packaging capacity. TSMC also pointed out that the demand for TSMC’s advanced packaging capacity far exceeds the existing capacity, and it is forced to increase production as quickly as possible. Chairman Mark Liu stated that the current investment in R&D focuses on two legs, namely 3D IC (chip stacking) and advanced packaging.

At present, three-quarters of TSMC’s R&D expenditure is used for advanced processes, and one quarter for mature and special processes, with advanced packaging falling under mature and special processes.

(Photo credit: TSMC)

The surge in AIGC and new technologies such IoT, AI, 5G, AR/VR are driving a huge demand for computational power of high-end chips. This has been even outpacing the performance increase offered by the long-standing Moore’s Law, ushering in a “post-Moore” era where revolutions in advanced chip design are crucial.

Over recent years, chiplet design has seemingly become the mainstream approach for upgrading high-end chips. The concept is to allow more transistors on a single chip, effectively increasing the production yield of high-end chips while reducing overall costs.

By the large, major IC players have all jumped on board. Even Apple has joined the game by releasing their M1 Ultra SoC using the chiplet concept, which doubles computational performance by integrating two M1 Max units in a single chip.

The CPU sector is definitely a clear demonstration of this trend:

• AMD took the leap with chiplet design in their 2nd-gen EPYC CPUs, doubling the computing cores from 32 to 64 within two years, while slashing costs by up to half. The company has extended this approach to their 4th-gen EPYC CPUs and even pioneered the GPU Navi 31, the first of its kind to use chiplets.
• Intel started incorporating chiplets into their Lakefield series SoC in 2020. Looking ahead, their upcoming CPUs like the Meteor Lake set for 2023, and Arrow Lake and Lunar Lake scheduled for 2024, will all use chiplet design.

Transition from Bumping to Hybrid Bonding

Our analysis in “Chiplet Design: A Real Game-Changer for Substrates” laid out the comprehensive impact of the evolution of chiplet technology on substrates. In fact, chiplets have already caused a significant disruption to the most advanced semiconductor packaging technologies, necessitating the transition towards advanced 2.5D and 3D packaging technologies.

The bottleneck of advanced packaging lies in the chiplets’ interconnections, with bump and microbump still being the key technology for linking chips and forming I/O joints. These connection densities are hard to enhance, thus limiting the overall chip’s transmission speed. In addition, the more chiplets being stacked, the bigger the chip volume gets. The challenge is how to limit the chip size within a specific range, considering the current technical constraints.

Therefore, copper-to-copper hybrid bonding, also known as DBI (Direct Bond Interconnect), has been emerging as the key technology route that overcomes major hurdles in chiplet integration from the bottom-up.

Unlike bumping technology, hybrid bonding significantly shrinks the I/O joint space. The future transmission demand requires the I/O joint space between chiplets to be less than 10µm. While bumping is limited to around 20µm, hybrid bonding can take this down to an impressive 1µm or even less. This also means more I/O joints can be fitted in the same chip size – even reaching up to millions on a mere 1cm2 chip.

On top of this, hybrid bonding only adds an extra 1-2µm of thickness, compared to the 10-30µm of microbump, thereby helping reduce the thickness of stacked chips.

To put it simply, hybrid bonding can boost transmission efficiency, minimize energy usage with higher density of copper joints, manage chip volume, and even cut down on material costs.

The Race for Advanced Packaging Is Kicking Off

Moving forward, hybrid bonding is set to become the key technology supporting the continuous development of chiplet design and 3D packaging. This has been exemplified by TSMC’s front-end So IC packaging technology which is based on hybrid bonding. This puts AMD, a key customer of TSMC, in a favorable position to get ahead.

From AMD’s roadmap of 3D V-Cache technology, they have stacked SRAM on top of CCX (CPU Complex), and gradually integrated it into Milan-X series, the EPYC server CPUs, and Ryzen series, the consumer-grade CPUs, over the past two years. This has significantly improved performance and power consumption as a whole.

Not to be outdone, this year Intel also launched their Foveros Direct packaging technology, which is also based on hybrid bonding route. Assuming everything proceeds smoothly, we can anticipate the release of CPUs utilizing Foveros Direct technology by 2024.

As we look at the current products, AMD’s hybrid bonding apparently focuses on stacking SRAM and computing units at the moment. However, as CPU leaders deepen their understanding of this technology, the application field is expected to further expand. In other words, the future of hybrid bonding solutions stacking multiple computation units is just around the corner.

Samsung recently announced that they will ahead of TSMC in the foundry market within 5 years. At the same time, Intel also claimed to become the second-largest player in the market before 2030. Currently, both Samsung and TSMC are adapting 3nm process to do the chip manufacturing, with the technology of GAA(Samsung) and FinFET(TSMC) respectively.

Samsung sees GAA technology as a crucial key to surpassing TSMC. Currently, Samsung’s 4nm lags behind TSMC by about 2 years, and its 3nm is about a year behind. However, this situation will change when TSMC turns to 2nm. Industry insider sources indicate that TSMC plans to use GAA technology in 2nm process, and Samsung believes that they can seize the chance to catch up with TSMC since TSMC may have a hard time when turning to 2nm process.

Industry insiders have revealed that AMD has shifted some of its 4nm CPU chip orders from TSMC to Samsung. It is reported that AMD has signed an agreement with Samsung to manufacture some of its mobile SoC by using Samsung’s 4nm node, and Samsung may also manufacture AMD’s Chromebook APU.

The Fight in the Foundry Market is On

According to TrendForce, the top 10 global foundry players in 4Q22 with TSMC account for 58.5% of market share by revenue, far ahead of Samsung’s 15.8%. Industry insiders suggest that Samsung still has a long way to go to catch up with TSMC. Some sources say that TSMC’s 2nm process will be mass-produced as scheduled in 2025, while Samsung’s plans are still to be observed.

Intel is also striving for the top spot in the wafer foundry market. Since the beginning of 2021, Intel has implemented a series of measures in its foundry business after announcing its “IDM 2.0” strategy. Last July, Intel stated that it will manufacture chips for MediaTek, and the first batch of products will be produced within the next 18 to 24 months using more mature manufacturing technology (Intel 16). In addition, Intel said that Qualcomm and Nvidia are also interested in having them manufacture their chips. To regain its leading edge in chip manufacturing, Intel has unveiled its 5 process technology stages to be launched in the next few years, including 10nm, 7nm, 4nm, 3nm, and 20A.

And TSMC has no competitive relationship with their clients by not doing the wafer design, apparently, this is also a significant advantage for TSMC and other foundry manufacturers. In recent years, more companies have recognized the importance and highly profitable nature of foundry manufacturing, leading to the independent establishment of foundry manufacturing operations. Samsung and Intel have also followed this trend, as foundry manufacturing can optimize production technology and provide major companies with more opportunities for trial and error.