According to a report from Tom’s Hardware citing industry sources, it’s indicated that Chinese memory giant ChangXin Memory Technologies (CXMT) has started mass production of HBM2. If confirmed, this is approximately two years ahead of the expected timeline, although the yield rate for HBM2 is still uncertain.

Earlier, Nikkei once reported that CXMT had begun procuring equipment necessary for HBM production, estimating it would take one to two years to achieve mass production. Currently, CXMT has ordered equipment from suppliers in the U.S. and Japan, with American companies Applied Materials and Lam Research having received export licenses.

Reportedly, HBM2 has a per-pin data transfer rate of approximately 2 GT/s to 3.2 GT/s. Producing HBM2 does not require the latest lithography techniques but does demand enough manufacturing capacity.

The process involves using through-silicon vias (TSV) to vertically connect memory components, which is rather complex. However, packaging the HBM KGSD (known good stack die) modules is still less intricate than manufacturing traditional DRAM devices using a 10nm process.

CXMT’s DRAM technology is said to be lagging behind that of Micron, Samsung, and SK hynix. These three companies have already started mass production of HBM3 and HBM3e and are preparing to advance to HBM4 in the coming years.

There also are reports indicating that Huawei, the Chinese tech giant subject to US sanctions, looks to collaborate with other local companies to produce HBM2 by 2026. Per a previous report from The Information, a group led by Huawei aimed at producing HBM includes Fujian Jinhua Integrated Circuit.

Moreover, since Huawei’s Ascend 910 series processors use HBM2, it has made HBM2 a crucial technology for advanced AI and HPC processors in China. Therefore, local manufacturing of HBM2 is a significant milestone for the country.

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(Photo credit: CXMT)

DRAM giant Nanya Technology held its shareholder meeting earlier today, during which Chairman Chia-Chau Wu reported on the company’s operations. According to a report from UDN, He mentioned that despite challenges such as unfavorable market conditions, geopolitical tensions, and the US-China trade conflict, Nanya Technology experienced a transition from profit to loss last year.

Nevertheless, the company continues to possess strong technological capabilities. This year, Nanya plans to introduce more products using the 10nm 1B process. Additionally, the 10nm 1C process is set to complete its first product design by the end of this year and begin trial production early next year. In 2026, Nanya will introduce new facilities, and by integrating miniaturization and Through-Silicon Via (TSV) processes, it will enter the high-capacity DRAM module market to meet the demand from the server market.

Wu emphasized that the 1B process products are Nanya Technology’s key expansion focus this year. In addition to promoting 8Gb/4Gb DDR4 to the personal computer and bare die application markets, the 16Gb DDR5 will initially target mainstream markets, including personal computers and servers.

Wu further highlighted that Nanya Technology continues to invest in research and development during the industry’s adjustment period to strengthen its future competitiveness.

Currently, in addition to developing three products under the second-generation 10nm (1B) process, Nanya Technology is also developing four other products: 16Gb DDR5 and miniaturized versions, 16Gb LPDDR4, 16Gb LPDDR5, and 4Gb DDR3, which will also gradually enter trial production.

He added that this year, Nanya Technology will simultaneously develop Through-Silicon Via (TSV) process technology. In the future, by combining the miniaturized DDR5 with the TSV process, Nanya aims to produce high-capacity DRAM modules to meet the demand of the server market.

Furthermore, the third-generation 10nm (1C) process technology is on track, with the design of the first 16Gb DDR5 product expected to be completed by the end of the year and trial production beginning early next year.

To support the transition to the 1B process and the construction of new facilities, Nanya Technology’s capital expenditure for this year is approximately TWD 26 billion (roughly USD 805.2 million), with less than half of the budget allocated to production equipment.

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(Photo credit: Nanya Technology)

In response to the demands of high-performance computing, AI, 5G, and other applications, the shift towards chiplet and the incorporation of HBM memory has become inevitable for advanced chips. As a result, packaging has transitioned from 2D to 2.5D and 3D formats.

With chip manufacturing advancing towards more advanced process nodes, the model of directly packaging chips using advanced packaging technology from wafer foundries has emerged. However, this approach also signifies that wafer foundries will encroach upon certain aspects of traditional assembly and testing, leading to ongoing discussions about the ‘threat’ to traditional assembly and test firms since TSMC’s entry into advanced packaging in 2011.

But is this perspective accurate?

In fact, traditional assembly and test firms remain competitively positioned. Firstly, numerous electronic products still rely on their diverse traditional packaging techniques. Particularly, with the rapid growth of AIoT, electric vehicles, and drones, the required electronic components often still adopt traditional packaging methods. Secondly, faced with wafer foundries actively entering the advanced packaging domain, traditional assembly and test firms have not been idle, presenting concrete solutions to the challenge.

Advanced Packaging Innovations by Traditional Assembly and Test Firms

Since 2023, AI and AI server trends have rapidly emerged, driving the demand for AI chips. TSMC’s 2.5D advanced packaging technology, known as CoWoS, has played a pivotal role. However, the sudden surge in demand stretched TSMC’s capacity. In response, major traditional assembly and test firms such as ASE and Amkor have demonstrated their technical prowess and have no intention of being absent from this field.

For instance, ASE’s FOCoS technology enables the integration of HBM and ASIC. It restructures multiple chips into a fan-out module, which is then placed on the substrate, achieving the integration of multiple chips. Their FOCoS-Bridge technology, unveiled in May this year, utilizes silicon bridges (Si Bridge) to accomplish 2.5D packaging, bolstering the creation of advanced chips required for applications like AI, data centers, and servers.

Additionally, SPIL, a subsidiary of ASE, offers the FO-EB technology, a powerful integration of logic IC and HBM. As depicted below, this technology eschews silicon interposers, utilizing silicon bridges and redistribution layers (RDL) for connections, similarly capable of 2.5D packaging.

Another major player, Amkor, has not only collaborated with Samsung to develop the H-Cube advanced packaging solution but has also long been involved in ‘CoWoS-like technology.’ Through intermediary layers and through-silicon via (TSV) technology, Amkor can interconnect different chips, also possessing 2.5D advanced packaging capabilities.

China’s major assembly and test firm, Jiangsu Changjiang Electronics Technology (JCET), employs the XDFOI technology, integrating logic ICs with HBM through TSV, RDL, and microbump techniques, aimed at high-performance computing.

Given the recent surge in demand for high-end GPU chips, TSMC’s CoWoS capacity has fallen short, and NVIDIA is actively seeking support from second or even third suppliers. The ASE Group and Amkor have secured partial orders through their packaging technologies. This clearly illustrates that traditional assembly and test firms, even when faced with the entry of wafer foundries into the advanced packaging domain, still possess the capability to compete.

In terms of product types, wafer foundries focus on advanced packaging technology for major players like NVIDIA and AMD. Meanwhile, other products not in the highest-end category still opt for traditional assembly and test firms like ASE, Amkor, and JCET for manufacturing. Overall, with their presence in advanced packaging, as well as a hold on the expanding existing packaging market, traditional assembly and test firms continue to maintain their market competitiveness.

(Photo credit: Amkor)

Over the past few decades, semiconductor manufacturing technology has evolved from the 10,000nm process in 1971 to the 3nm process in 2022, driven by the need to increase the number of transistors on chips for enhanced computational performance. However, as applications like artificial intelligence (AI) and AIGC rapidly advance, demand for higher core chip performance at the device level is growing.

While process technology improvements may encounter bottlenecks, the need for computing resources continues to rise. This underscores the importance of advanced packaging techniques to boost the number of transistors on chips.

In recent years, “advanced packaging” has gained significant attention. Think of “packaging” as a protective shell for electronic chips, safeguarding them from adverse environmental effects. Chip packaging involves fixation, enhanced heat dissipation, electrical connections, and signal interconnections with the outside world. The term “advanced packaging” primarily focuses on packaging techniques for chips with process nodes below 7nm.

Amid the AI boom, which has driven demand for AI servers and NVIDIA GPU graphics chips, CoWoS (Chip-on-Wafer-on-Substrate) packaging has faced a supply shortage.

But what exactly is CoWoS?

CoWoS is a 2.5D and 3D packaging technology, composed of “CoW” (Chip-on-Wafer) and “WoS” (Wafer-on-Substrate). CoWoS involves stacking chips and then packaging them onto a substrate, creating a 2.5D or 3D configuration. This approach reduces chip space, while also lowering power consumption and costs. The concept is illustrated in the diagram below, where logic chips and High-Bandwidth Memory (HBM) are interconnected on an interposer through tiny metal wires. “Through-Silicon Vias (TSV)” technology links the assembly to the substrate beneath, ultimately connecting to external circuits via solder balls.

The difference between 2.5D and 3D packaging lies in their stacking methods. 2.5D packaging involves horizontal chip stacking on an interposer or through silicon bridges, mainly for combining logic and high-bandwidth memory chips. 3D packaging vertically stacks chips, primarily targeting high-performance logic chips and System-on-Chip (SoC) designs.

When discussing advanced packaging, it’s worth noting that Taiwan Semiconductor Manufacturing Company (TSMC), rather than traditional packaging and testing facilities, is at the forefront. CoW, being a precise part of CoWoS, is predominantly produced by TSMC. This situation has paved the way for TSMC’s comprehensive service offerings, which maintain high yields in both fabrication and packaging processes. Such a setup ensures an unparalleled approach to serving high-end clients in the future.

Applications of CoWoS

The shift towards multiple small chips and memory stacking is becoming an inevitable trend for high-end chips. CoWoS packaging finds application in a wide range of fields, including High-Performance Computing (HPC), AI, data centers, 5G, Internet of Things (IoT), automotive electronics, and more. In various major trends, CoWoS packaging is set to play a vital role.

In the past, chip performance was primarily reliant on semiconductor process improvements. However, with devices approaching physical limits and chip miniaturization becoming increasingly challenging, maintaining small form factors and high chip performance has required improvements not only in advanced processes but also in chip architecture. This has led to a transition from single-layer chips to multi-layer stacking. As a result, advanced packaging has become a key driver in extending Moore’s Law and is leading the charge in the semiconductor industry.

(Photo credit: TSMC)