UMC has reportedly received a contract to manufacture crucial chips for Apple’s upcoming iPhone antenna modules. According to a report from Economic Daily News, the production volume is said to be in the tens of thousands.

Regarding this, UMC does not respond to specific customer and market rumors. It is reported that the orders from UMC this time come from Qorvo, a supplier for Apple’s power amplifier (PA).

Qorvo designs new iPhone antenna components for Apple, integrating new chips and supplying them with Qorvo power amplifiers. These new chips adopt UMC’s 3DIC technology and are manufactured by UMC.

Per the report citing industry sources, it has revealed that the chips Qorvo outsourced UMC this time are products of Anokiwave, a wireless communication chip factory that Qorvo recently merged with early this year. They will be integrated into the design of new iPhone antenna modules and are currently gradually increasing in volume.

As smartphones gradually integrate AI functionality, the sources cited in the same report also reveal that Apple is enhancing efficiency by adopting a new design for the next generation iPhone antenna module. They are incorporating products from Anokiwave, which was acquired by Qorvo earlier this year, to enhance iPhone reception capabilities.

With Qorvo leveraging Anokiwave’s products and partnering with UMC for manufacturing, UMC secures critical component chip orders for the iPhone once again. Previously, UMC also manufactured driver IC chips for Apple through NovaTek.

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• [News] UMC Seamlessly Integrates Key 12-Nanometer Technology as Intel Joins Forces
• [News] First Quarter Market Outlook Affected by Off-Season Effects, Three Foundries Discuss Industry Conditions

(Photo credit: Apple)

As Intel’s January announced the collaboration with UMC on the 12-nanometer process platform, UMC’s Co-General Manager, Jason Wang, led a team to support Intel’s IFS event.

Cited by Commercial Times in its report, Wang emphasized that UMC’s existing customers would have more production location options and benefit from the platform strategy. UMC will seamlessly transition from the 28/22-nanometer to the critical 12-nanometer.

Followed by joint interviews to share insights into the future strategies of both parties, Wang stated that in the face of rapid changes and challenges in the external environment, industries need to strengthen their cooperative relationships and seize opportunities for collaboration.

Intel and UMC announced their collaboration at the end of January, focusing on the development of a shared platform for the 12-nanometer process. In the future, UMC will be able to expand its orders for the front-end of the 12-nanometer process, while Intel will secure orders for the 12-nanometer wafer manufacturing.

Jason Wang emphasized that UMC has a comprehensive solution for the 28/22-nanometer, with demand trending towards stability. However, due to past limitations in resource allocation , UMC has paused at the 14/16-nanometer. Advancing to more advanced processes is just a matter of timing.

Wang further stated that both parties will focus on creating customer value, breaking frameworks, and innovating in cooperation. The two companies complement each other’s strengths, accelerating the timeline for technological development and expanding their global footprint.

Wang revealed that Intel has already included UMC’s 12-nanometer process in its product roadmap and has begun deep collaboration. UMC has deployed personnel to oversee this, with Intel leveraging UMC’s know-how in management.

Additionally, the collaboration involves revenue sharing rather than the rumored licensing fees. They anticipate completing the Process Design Kit (PDK) by next year and achieving mass production by the end of 2026.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits at the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

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• [News] Intel Foundry Unveils its Expanded Process Roadmap for AI Era at Direct Connect 2024 Event
• Strategic Collaboration Between Intel and UMC to Optimize FinFET Foundry Market with Existing Resources, Says TrendForce

(Photo credit: Intel)

Foundry is a crucial sector in the semiconductor industry and a focal point of attention for many professionals in the industry. Recently, three foundries have released their outlook for the first half of 2024, all indicating a cautious outlook for the first quarter.

According to Taiwanese News outlet Commercial Times, United Microelectronics Corporation (UMC), Powerchip Semiconductor Manufacturing Corporation (PSMC), and Vanguard International Semiconductor Corporation (VIS) anticipate a subdued first quarter due to factors such as off-season effects and holidays.

With conservative estimates on wafer shipments, average selling prices (ASP), and gross margins for the first quarter, there remains a high likelihood of a continued decline in performance compared to the previous quarter.

• VIS: Visibility of the Market Conditions Limited to about Only 2 to 3 Months

VIS stated in a recent conference that semiconductor demand entered the traditional off-season at the beginning of the year.

It is expected that the supply chain will continue inventory adjustments and maintain a cautious approach to orders. Assuming an average exchange rate of NTD 30.9, shipments are expected to decrease by 6-8% quarterly, with average selling prices roughly remaining flat and gross margins falling between 21-23%.

VIS believes that the industry is still undergoing inventory adjustments, and the overall economic situation remains sluggish. Currently, the visibility of the market is limited to only two to three months. In the first quarter, due to continuous inventory adjustments in the supply chain and a cautious approach to ordering, capacity utilization will decrease to 50%.

In addition, regarding the investment in 12-inch fabs, VIS Chairman Leuh Fang stated that due to the significant investment required for 12-inch fabs, there must be definite demand and leading technological sources before deciding to proceed with construction.

Currently, the decision is still in the cautious evaluation stage, and no plants will be built hastily until the technology sources are confirmed.

• PSMC: A Conservative Outlook

PSMC’s General Manager, Brian Shieh, stated during a mid-January earnings call that the company expects a seasonal decline of approximately 5-6% in revenue for the first quarter due to fewer working days.

Regarding inventory, PSMC noted that client inventory levels are currently at normal, with the semiconductor manufacturing segment performing relatively well. It is anticipated that capacity utilization rates for the first quarter of 2024 could rebound to 70% to 75%, offering promising prospects for operations in the latter half of the year.

Overall, PSMC aims for a capacity utilization rate of over 90% for the full year, with the goal of continuously filling the new capacity at the Tongluo plant in the second half of the year. The company estimates that the Tongluo plant can be fully operational in the latter half of the year, primarily focusing on 55nm and 40nm logic products.

• UMC: Visibility of the Market Conditions for 2024 is Relatively Limited

UMC forecasts a modest increase of 2-3% in wafer shipments for the first quarter of 2024, with ASP quoted in USD expected to decrease by 5%, leading to a slight decline in gross margin to around 30%. This is primarily attributed to adjustments in pricing and changes in product mix. Capacity utilization is anticipated to remain at low 60%.

In terms of production lines, stable demand is projected for communication and consumer sectors, maintaining flat revenue trends, while automotive and industrial segments are expected to undergo inventory adjustments, resulting in a seasonal decline in revenue for the first quarter of 2024.

UMC estimates that the revenue contribution from special processes will reach 30% in the first quarter of this year, with sales from a predominant single customer making a significant contribution.

Regarding the medium to long-term outlook for the full year, UMC stated that the semiconductor market is expected to grow at a mid-single-digit rate annually, while the foundry industry is forecasted to grow at a high single-digit rate, approaching 10%.

UMC’s revenue is expected to align closely with the growth rate of the wafer foundry industry. UMC holds a cautiously optimistic outlook for demand in 2024, as smartphone and PC inventory levels returned to relatively normal levels in the fourth quarter of 2023.

Additionally, on January 25th of this year, Intel and UMC announced a collaboration to develop 12nm technology. Both parties will share the expenses, with Intel taking charge of operating the facility.

UMC stated that the capacity expansion will significantly impact the company’s operational performance once production starts. The technology is expected to enter the Process Design Kit (PDK) stage in 2025, begin trial production in 2026, and commence supply in 2027. The 12nm technology represents a potential market worth billions, and the collaboration does not include IP licensing.

Regarding this matter, TrendForce believes that this partnership, which leverages UMC’s diversified technological services and Intel’s existing factory facilities for joint operation, not only aids Intel in transitioning from an IDM to a foundry business model but also brings a wealth of operational experience and enhances manufacturing flexibility.

For UMC, this collaboration is a game-changer as it allows the company to agilely leverage FinFET capacity without the pressure of heavy capital investments.

This move positions UMC to carve out a unique niche in the fiercely competitive mature process market. Furthermore, by co-managing Intel’s US facility, UMC can expand its global footprint, smartly diversifying geopolitical risks. This partnership is shaping up to be a win-win for both.

Overall, TrendForce views this alliance as a significant step. UMC brings its plentiful experience in mature processes, while Intel contributes its advanced technological prowess.

This partnership is not just about mutual benefits at the 10nm process level; it’s a watchpoint for potentially deeper and more extensive collaboration in their respective fields of expertise. In the dynamic world of semiconductor manufacturing, this Intel-UMC alliance is a fascinating development to keep an eye on.

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• [News] NVIDIA and AMD Clash in AI Chip Market, as TSMC Dominates Orders with Strong Momentum in Advanced Processes
• [News] Intel Teams Up with UMC to Pursue 12-Nanometer Technology, Production Expected by 2027

(Photo credit: UMC)

As reported by Indian media Economic Times, India’s Tata group may collaborate with Taiwanese semiconductor foundries like UMC or PSMC to establish the first fab in India, initially producing mature process chips with a planned monthly capacity of 25,000 wafers. If successful, it would mark Taiwan’s semiconductor industry’s first venture into India.

The report addresses the recent escalation of geopolitical tensions, which has led to India’s issues in local chip manufacturing. Thus, India is reportedly looking for major foundries to establish fabs in India, given its substantial demand for semiconductors.

Although neither UMC nor PSMC has formally announced investments in India, as per the Economic Times of India, Tata Group may collaborate with Taiwanese foundries like UMC or PSMC to establish a semiconductor fab in Dholera, Gujarat, India.

Initially targeting the 65-nanometer mature process, the aforementioned fab is expected a monthly capacity of 25,000 wafers, with plans for future upgrades to 48-nanometer and 28-nanometer processes, supporting the production of GPUs, consumer electronics, and Internet of Things (IoT) applications in the coming years.

According to sources cited by the Economic Times of India, Tata Group has finalized the details of the land for this factory and groundbreaking may occur soon. However, Tata Group’s entry into the 28-nanometer process may take some time as it needs to ensure sufficient orders for mature processes in the Indian market.

PSMC Chairman Frank Huang revealed in early 2023 that he had received an invitation to assist in setting up a plant in India, but he did not disclose the details or the inviting party at that time.

PSMC has yet to announce any investments in India.

Instead, they have partnered with the Japanese company SBI Holdings, Inc. to establish a joint venture for a 12-inch fab in Japan. This venture will be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture. It is planned to produce chips ranging from 28 to 55 nanometers, with an initial monthly capacity of 10,000 wafers and an ultimate goal of 40,000 wafers, focusing on the automotive chip market.

UMC has also been reportedly sending representatives to India for inspections and discussions regarding the opportunity to establish facilities there, as disclosed by Indian media in recent years.

However, UMC has yet to take any action to invest in India. Instead, in 2022, the company initiated its strategy to establish a new 22-nanometer fab in Singapore, with plans for completion by the end of the second quarter of this year and mass production slated to begin in early 2025, with an initial monthly capacity of 20,000 to 30,000 wafers.

UMC and PSMC didn’t comment on the matter on February 20th. “UMC does not comment on market speculations.” a spokesperson for UMC said, cited by Economic Times.

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• [News] Tata Reportedly Partners with Pegatron for iPhone Assembly in India
• [News] iPhone Manufacturing Dominance: One Leader, Two Contenders, One Challenger

(Photo credit: Tata Group)

With the flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing, modern society has an increasingly high demand for computing power.

Moreover, with the advancement beyond 3 nanometers, wafer sizes have encountered scaling limitations and manufacturing costs have increased. Therefore, besides continuing to develop advanced processes, the semiconductor industry is also exploring other ways to maintain chip size while ensuring high efficiency.

The concept of “heterogeneous integration” has become a contemporary focus, leading to the transition of chips from single-layer to advanced packaging with multiple layers stacked together.

The term “CoWoS” can be broken down into the following definitions: “Cow” stands for “Chip-on-Wafer,” referring to the stacking of chips, while “WoS” stands for “Wafer-on-Substrate,” which involves stacking chips on a substrate.

Therefore, “CoWoS” collectively refers to stacking chips and packaging them onto a substrate. This approach reduces the space required for chips and offers benefits in reducing power consumption and costs.

Among these, CoWoS can be further divided into 2.5D horizontal stacking (most famously exemplified by TSMC’s CoWoS) and 3D vertical stacking versions. In these configurations, various processor and memory modules are stacked layer by layer to create chiplets. Because its primary application lies in advanced processes, it is also referred to as advanced packaging.

According to TrendForce’s data, it has provided insights into the heat of the AI chip market. In 2023, shipments of AI servers (including those equipped with GPU, FPGA, ASIC, etc.) reached nearly 1.2 million units, a 38.4% increase from 2022, accounting for nearly 9% of the overall server shipments.

Looking ahead to 2026, the proportion is expected to reach 15%, with a compound annual growth rate (CAGR) of AI server shipments from 2022 to 2026 reaching 22%.

Due to the advanced packaging requirements of AI chips, TSMC’s 2.5D advanced packaging CoWoS technology is currently the primary technology used for AI chips.

GPUs, in particular, utilize higher specifications of HBM, which require the integration of core dies using 2.5D advanced packaging technology. The initial stage of chip stacking in CoWoS packaging, known as Chip on Wafer (CoW), primarily undergoes manufacturing at the fab using a 65-nanometer process. Following this, through-silicon via (TSV) is carried out, and the finalized products are stacked and packaged onto the substrate, known as Wafer on Substrate (WoS).

As a result, the production capacity of CoWoS packaging technology has become a significant bottleneck in AI chip output over the past year, and it remains a key factor in whether AI chip demand can be met in 2024. Foreign analysts have previously pointed out that NVIDIA is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology.

This includes NVIDIA’s H100 GPU, which utilizes TSMC’s 4-nanometer advanced process, as well as the A100 GPU, which uses TSMC’s 7-nanometer process, both of which are packaged using CoWoS technology. As a result, NVIDIA’s chips account for 40% to 50% of TSMC’s CoWoS packaging capacity. This is also why the high demand for NVIDIA chips has led to tight capacity for TSMC’s CoWoS packaging.

TSMC’s Expansion Plans Expected to Ease Tight Supply Situation in 2024

During the earnings call held in July 2023, TSMC announced its plans to double the CoWoS capacity, indicating that the supply-demand imbalance in the market could be alleviated by the end of 2024.

Subsequently, in late July 2023, TSMC announced an investment of nearly NTD 90 billion (roughly USD 2.87 billion) to establish an advanced packaging fab in the Tongluo Science Park, with the construction expected to be completed by the end of 2026 and mass production scheduled for the second or third quarter of 2027.

In addition, during the earnings call on January 18, 2024, TSMC’s CFO, Wendell Huang, emphasized that TSMC would continue its expansion of advanced processes in 2024. Therefore, it is estimated that 10% of the total capital expenditure for the year will be allocated towards expanding capacity in advanced packaging, testing, photomasks, and other areas.

In fact, NVIDIA’s CFO, Colette Kress, stated during an investor conference that the key process of CoWoS advanced packaging has been developed and certified with other suppliers. Kress further anticipated that supply would gradually increase over the coming quarters.

Regarding this, J.P. Morgan, an investment firm, pointed out that the bottleneck in CoWoS capacity is primarily due to the supply-demand gap in the interposer. This is because the TSV process is complex, and expanding capacity requires more high-precision equipment. However, the long lead time for high-precision equipment, coupled with the need for regular cleaning and inspection of existing equipment, has resulted in supply shortages.

Apart from TSMC’s dominance in the CoWoS advanced packaging market, other Taiwanese companies such as UMC, ASE Technology Holding, and Powertek Technology are also gradually entering the CoWoS advanced packaging market.

Among them, UMC expressed during an investor conference in late July 2023 that it is accelerating the deployment of silicon interposer technology and capacity to meet customer needs in the 2.5D advanced packaging sector.

UMC Expands Interposer Capacity; ASE Pushes Forward with VIPack Advanced Packaging Platform

UMC emphasizes that it is the world’s first foundry to offer an open system solution for silicon interposer manufacturing. Through this open system collaboration (UMC+OSAT), UMC can provide a fully validated supply chain for rapid mass production implementation.

On the other hand, in terms of shipment volume, ASE Group currently holds approximately a 32% market share in the global Outsourced Semiconductor Assembly and Test (OSAT) industry and accounts for over 50% of the OSAT shipment volume in Taiwan. Its subsidiary, ASE Semiconductor, also notes the recent focus on CoWoS packaging technology. ASE Group has been strategically positioning itself in advanced packaging, working closely with TSMC as a key partner.

ASE underscores the significance of its VIPack advanced packaging platform, designed to provide vertical interconnect integration solutions. VIPack represents the next generation of 3D heterogeneous integration architecture.

Leveraging advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies, VIPack enables customers to integrate multiple chips into a single package, unlocking unprecedented innovation in various applications.

Powertech Technology Seeks Collaboration with Foundries; Winbond Electronics Offers Heterogeneous Integration Packaging Technology

In addition, the OSAT player Powertech Technology is actively expanding its presence in advanced packaging for logic chips and AI applications.

The collaboration between Powertech and Winbond is expected to offer customers various options for CoWoS advanced packaging, indicating that CoWoS-related advanced packaging products could be available as early as the second half of 2024.

Winbond Electronics emphasizes that the collaboration project will involve Winbond Electronics providing CUBE (Customized Ultra-High Bandwidth Element) DRAM, as well as customized silicon interposers and integrated decoupling capacitors, among other advanced technologies. These will be complemented by Powertech Technology’s 2.5D and 3D packaging services.

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• [News] AMD Eyes CoWoS-like Supply for AI Chips with TSMC Full Capacity
• [News] Samsung Boosts 2.5D Packaging Equipment to Compete for TSMC’s CoWoS Orders

(Photo credit: TSMC)