If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.

On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.

Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.

What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.

N3 Family

TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.

TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.

Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.

Intel’s Lunar Lake/ Arrow Lake

At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.

Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.

In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.

NVIDIA’s Rubin

On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.

Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

AMD’s MI 325X/ MI350

On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.

AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.

Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.

When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.

In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:

N2 Family

The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.

In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.

Read more

• [News] TSMC’s Advanced Packaging Capacity Fully Booked by NVIDIA and AMD Through Next Year
• [News] Samsung Reportedly Doing Its Utmost to Win 3nm GPU Orders from NVIDIA

(Photo credit: TSMC)

Qualcomm President & CEO Cristiano Amon, at COMPUTEX 2024, showcased devices powered by Snapdragon X Elite and Snapdragon X Plus processors, claiming them to be the only PCs capable of delivering Copilot+ PC experiences. Afterwards, during a media briefing, he disclosed Qualcomm’s plans on a dual-sourcing production strategy, indicating that the cooperation with Samsung has been considered, Korean media outlet Business Korea reported.

According to a previous report by Wccftech, Qualcomm’s Snapdragon 8 Gen 4, targeting to be launched in October, is rumored to utilize TSMC’s N3E node. However, the possibility of diversifying the production sources for Qualcomm’s “Snapdragon 8 Gen 5” smartphone chip has recently become a hot topic.

Regarding Qualcomm’s potential dual-sourcing policy, Amon emphasized that the primary focus should be on TSMC’s foundry production. However, he expressed willingness to collaborate with both TSMC and Samsung Electronics, according to Business Korea.

Initially, Samsung’s foundry was tasked with producing the first-generation Snapdragon 8 chip. However, it is rumored that overheating issues prompted Qualcomm to assign the following generations to be manufactured by TSMC.

Nonetheless, according to Business Korea, the recent launch of the Snapdragon X Elite, extensively integrated with Microsoft’s CoPilot+ PC, has sparked greater demand, which has prompted Qualcomm to reassess its collaboration with Samsung.

According to a previous report by Wccftech, it is likely that the Samsung’s 2nm technology will be utilized for the Snapdragon 8 Gen 5 in the Galaxy S26 series.

Read more

• [News] Samsung Fails to Secure Qualcomm’s 3nm Orders for the Coming Year, Dual Foundry Strategy Postponed

(Photo credit: Qualcomm)

At TSMC’s 2024 Technology Symposium in late May, Kevin Zhang, TSMC Senior Vice President of Business Development, has shared the company’s latest development on advanced packaging. This article recaps the highlights in the forum, featuring TSMC’s breakthroughs regarding advanced packaging.

Advanced Packaging

SoW (System-on-Wafer Integration Technology)

SoW adopts TSMC’s InFO and CoWoS packaging technologies to integrate logic dies and HBM memory on the wafer. By doing so, TSMC aims to enhance performance and speed not just at the chip level, but the system level as well.

Currently, TSMC’s system-on-wafer manufactured with InFO technology has entered mass production. Afterwards, the company plans to develop and launch SOW using CoWoS technology to integrate SoC or SoIC, HBM, and other components together.

TSMC eyes its System-on-Wafer manufactured with the CoWoS technology to enter mass production in 2027, while its target applications would include AI and HPC, expanding the computational power needed for data centers of the next generation.

3DFabric

TSMC’s 3DFabric technology family includes three major platforms: SoIC, CoWoS, and InFO, encompassing both 2D and 3D front-end and back-end interconnect technologies.

SoIC

The SoIC platform offers two stacking solutions: SoIC-P (Bumped) and SoIC-X (Bumpless). The first solution, SoIC-P, is a micro-bump stacking solution suitable for cost-effective applications such as mobile devices.

The other solution, SoIC-X, adopts Hybrid Bonding, which is ideal for HPC and AI demands. The advantage of this solution is that the pitch between contacts can be reduced to a few micrometers (µm), increasing the interconnect interface between two chips while achieving a new level of interconnect density.

TSMC’s current bond pitch density with Hybrid Bonding has been reduced to 6 micrometers, and it aims to further reduce it 2 to 3 micrometers. In the meantime, the company has been advancing micro-bump technology, currently at over 30 micrometers, with the future goal of reducing it to the teens.

TSMC revealed that customer demand for SoIC-X technology has been increasing, with 30 customer design tape-outs expected by the end of 2026.

CoWoS / InFO

The CoWoS advanced packaging family includes three members: CoWoS-S, CoWoS-L, and CoWoS-R. The three platforms can mainly be differentiated by their intermediate layer materials, which may also affect the cost. In other words, CoWoS-S utilizes silicon interposer, CoWoS-L uses LSI (Local Silicon Interconnect), while CoWoS-R uses RDL (Redistribution Layer) wiring to connect small chips.

Depending on product requirements, SoIC chips can be integrated with either CoWoS or InFO. AMD’s MI300A / MI300 X is the first product to adopt SoIC-X and CoWoS technology.

One of the most well-known product which adopts TSMC’s CoWoS-L technology would be NVIDIA’s Blackwell AI accelerator, which integrates two SoCs using 5nm with eight HBM into one module.

Moreover, TSMC’s CoWoS technology integrates advanced SoCs/SoICs with HBM to meet the requirements of AI chips. Its SoIC has entered mass production through the CoWoS-S platform. Going forward, TSMC plans to develop a SoIC chip with an eight-time mask size (using the A16 process) and a CoWoS solution with 12 HBM stacks. This updated version is expected to enter mass production in 2027.

(Photo credit: TSMC)

In the past two years, the semiconductor industry has experienced a market downturn, a recovery slower than expected, and a cash crunch. Major companies such as Intel, TSMC, and Samsung, while continuing to advance their expansion projects, have been constantly adjusting and slowing down the pace and schedule of their fab construction to better serve their long-term development goals. It’s found that seven fabs worldwide are projected to delay construction.

• Intel’s 1nm Chip Plant in Germany and Ohio Plant in the US Delay Construction

According to a report from global media outlet Volksstimme, the construction of Intel’s Fab 29.1 and Fab 29.2 near Magdeburg, Germany, has been postponed due to pending approval of EU subsidies and the need to remove and reuse black soil. The date of commencement has been pushed from summer 2024 to May 2025.

Earlier reports indicated that the construction of this chip planr was initially expected to begin in 1H23, but due to subsidy delays, construction was put off to summer 2024. Moreover, the topsoil at the construction site cannot be cleared until May 2025 at the earliest.

It is reported that Intel’s Fab 29.1 and Fab 29.2 were originally scheduled to start operations by late 2027 and were expected to employ advanced manufacturing processes, potentially Intel 14A (1.4nm) and Intel 10A (1nm) process nodes. However, Intel now estimates that it will take four to five years to build these two plants, and production is expected to commence between 2029 and 2030.

• Samsung’s Chip Plant in Pyeongtaek, South Korea and Fab in Taylor, US Delay Construction

In February 2024, Samsung revealed that it had partially halted the construction of its fifth semiconductor plant in Pyeongtaek, Gyeonggi Province. Samsung originally planned to build six semiconductor plants on an 855,000 square meter site in Pyeongtaek, creating the world’s largest semiconductor hub. Currently, the P1, P2, and P3 plants at the Pyeongtaek park house the most advanced DRAM, NAND flash memory, and foundry production lines, while the P4 and P5 plants are under construction.

Samsung stated that the halt was for further inspection. However, industry sources have revealed that Samsung’s adjustment of the new production lines for P4 and P5 fabs is to prioritize the construction of the PH2 production line at P4 fab. It is reported that P4 plant might build PH3 production line to produce high-end DRAM to meet market demands.

Besides, South Korean media Businesskorea also revealed Samsung has postponed the mass production timeline of the fab in Taylor, Texas, US from late 2024 to 2026, which is possibly due to a slowdown in the wafer foundry market growth, and the delay was attributed to U.S. government subsidies and issues related to the complexities in gaining permits.

• TSMC Postponed the Production of Two Plants in Arizona, US

On April 9, TSMC announced the plan to build a third fab in Arizona. Once completed, this fab will use 2nm process or even more advanced technologies to manufacture wafers for customers. With this addition, TSMC’s total capital expenditure in Phoenix, Arizona, will exceed USD 65 billion.

Meanwhile, TSMC disclosed that their first fab in Arizona will start production in 1H25, using 4nm process. The second fab, initially announced to use 3nm process, will also incorporate the more advanced 2nm process, with mass production set to begin in 2028. This fab was announced in December 2020, which was originally scheduled to start mass production using 3nm process in 2026, primarily, but the latest schedule represents a delay of nearly two years from the original one.

As to the third fab planned to set up in Arizona, TSMC has not yet disclosed the date for construction. However, they mentioned that it will use 2nm process or more advanced ones, with production expected to commence in the late 2030s.

• Wolfspeed’s 8-Inch SiC Fab might Delay Construction to 2025

Wolfspeed’s 8-inch SiC fab in Ensdorf, Saarland planned to invest about EUR 2.75 billion, but the construction has been postponed. The project has already secured subsidies of EUR 360 million from the German federal government and EUR155 million from the Saarland government. In addition, Wolfspeed is also seeking financial assistance from the European Chips Act. ZF will provide Wolfspeed with several hundred million dollars of financial investment in exchange for a minority stake in the plant.

Industry sources indicate that Wolfspeed aims to secure more funding before the groundbreaking ceremony. If it fails to gain financial assistance from the European Chips Act, the project is very likely to be delayed. The plant was initially scheduled to start construction in summer 2024, but Wolfspeed CEO Gregg Lowe revealed that it might now begin in 2025.

Read more

• [News] Intel’s 1nm-class Fabs in Germany Reportedly Delayed Due to Black Soil Concerns and Pending EU Subsidy Approval
• [News] TSMC’s Nanjing Plant Reportedly Pushes for Indefinite Exemption From US Before the May 31 Deadline
  

(Photo credit: TSMC)

Intel has reportedly delayed its construction of Fab 29.1 and 29.2 in Magdeburg, Germany, as the new timeline now pushes the start of construction to May 2025, according to a report by tom’s Hardware, citing German media outlet Volksstimme.

However, the fabs could still become operational by late 2027 or early 2028 if the semiconductor giant expedites construction and tool installation, the report stated. The current scenario does seem challenging though, as the company has to deal with black soil removal issues and delays in subsidy approvals.

In June 2023, Intel reached an agreement with Germany, announcing the signing of an amended investment memorandum. The plan involves investing over EUR 30 billion to construct two new fabs in Magdeburg, of which the German federal government has agreed to provide a subsidy of EUR 10 billion, including incentives and subsidies from the European Chips Act and government initiatives.

Originally, construction was scheduled to begin in the first half of 2023 but was postponed to summer 2024 due to delays in subsidy approvals. Until recently, the EU Competition Authority has not yet approved the around EUR 10 billion subsidy.

The topsoil removal process, as required by law, thus, has been rescheduled to May 2025. In the meantime, Intel and the state are adjusting plans, focusing on infrastructure development and land acquisition to prepare for the delayed construction, according to the aforementioned reports.

Fab 29.1 and Fab 29.2 were initially planned to begin operations in late 2027, utilizing Intel’s 14A (1.4nm) and 10A (1nm) process nodes for specific products on Intel’s roadmap, the reports noted. Although Intel has some time to ramp up the fab even if it becomes ready by mid-2028, the schedule remains tight.

The report from Volksstimme even indicated that Intel now estimates it will take four to five years to build the two factories, with production potentially starting in 2029 or 2030.

On the other hand, regarding major semiconductor companies’ overseas expansion progress in Germany, in mid-May, TSMC confirmed that it will start construction of its first chip plant in Europe in Dresden, eastern Germany, in the fourth quarter of this year, with production expected to begin in 2027.

It is understood that TSMC’s fab in Germany will initially focus on the 22-nanometer process, mainly producing automotive microcontrollers. There is a possibility of expanding to produce more advanced chips in the future.

Read more

• [News] Intel Submits Conceptual Drawings for Fab Construction in Germany, Installing High-NA EUV Exposure Machines
• [News] TSMC Confirms Construction for Its First European Chip Plant to Commence in Q4, as Scheduled

(Photo credit: Intel)