On October 11th, Amkor announced the official opening of its factory located in the Yen Phong 2C Industrial Park in Bac Ninh Province, Vietnam. The new facility, occupying 57 acres, is set to become Amkor’s largest, with an investment of approximately $1.6 billion by 2035. The factory primarily focuses on providing advanced system-level packaging and testing solutions to meet the semiconductor industry’s demand for advanced packaging. However, the company has not disclosed the factory’s current production and capacity.

Multiple Players Pursue CoWoS

The ongoing AI trend continues to drive demand for Chip-on-Wafer-on-Substrate (CoWoS) technology, benefiting TSMC, which holds a significant share of CoWoS production orders. However, companies like ASE Group, Amkor, and UMC are also positioning themselves in the CoWoS packaging manufacturing space. Industry experts believe that given the current high demand for TSMC’s CoWoS production, part of this demand may potentially shift to Amkor’s factories.

Furthermore, the popular Nvidia AI chips, which are in high demand globally, utilize 2.5D packaging technology, a responsibility currently held by TSMC. Recently, Nvidia hinted at the mass production of new AI chips like the GH200 and general server chip L40S, with reports suggesting that L40S will not require 2.5D packaging. Instead, it will be shared among several backend packaging companies, including ASE, Amkor, and SPIL.

Industry source has noted the strong demand for CoWoS in the AI sector, and with TSMC’s CoWoS production capacity already unable to meet demand for several quarters, some demand may potentially shift to Amkor or Samaung’s facilities.

Amkor has announced plans to expand its advanced packaging CoWoS-like capacity. According to industry insiders, Amkor’s monthly production capacity for 2.5D advanced packaging is expected to reach approximately 3,000 wafers in early 2023, with estimates of reaching 5,000 wafers by the end of 2023 and aiming for a significant increase to 7,000 units by the end of 2024.

Additionally, ASE Group has announced its presence in advanced CoWoS-related packaging. With their fan-out chip-on-substrate (FOCoS-Bridge) packaging technology, ASE has been chosen by major chip design house to handle their backend packaging after CoW.

In mid-September, South Korean media reported that Samsung is set to introduce its FO-PLP 2.5D advanced packaging technology to catch up with TSMC in the field of advanced packaging for AI chips. Samsung’s Advanced Packaging (AVP) team began developing FO-PLP advanced packaging for 2.5D chip packaging, allowing the integration of System-on-Chip (SoC) and High Bandwidth Memory (HBM) into an interposer to create a complete chip.

It’s worth mentioning that Samsung’s FO-PLP 2.5D packaging is rectangular, while TSMC’s CoWoS 2.5D uses a circular substrate. Samsung’s FO-PLP 2.5D packaging avoids edge substrate losses and boasts higher production efficiency. However, due to the need to transplant chips from wafers onto rectangular substrates, the process is more complex.

CoWoS Demand Continues

CoWoS technology is a form of 2.5D and 3D packaging, where chips are stacked and then packaged onto a substrate, resulting in a 2.5D or 3D structure. This technology reduces chip space, while also decreasing power consumption and costs. CoWoS packaging is applied in high-performance computing, artificial intelligence, data centers, 5G, the Internet of Things, automotive electronics, and other fields.

TrendForce research indicates a growing demand for advanced packaging technologies for AI and HPC chips. Currently, TSMC’s CoWoS is the primary choice for AI server chip production. CoWoS packaging mainly consists of CoW (Chip on Wafer), integrating various logic ICs (such as CPUs, GPUs, ASICs, etc.) and HBM memory, while oS (On Substrate) integrates CoW elements using Solder bump interconnects and packages them on a substrate. These CoWoS packages become the primary computing units on server motherboards, together with other components like networks, storage, power supply units (PSUs), and other I/O units, forming complete AI server systems.

Explore more

• Advanced Packaging in High Demand, TSMC and OAST Increasing Equipment Orders
• Understanding the 3D Packaging Trends Pursued by TSMC, Intel and Samsung
• An In-Depth Explanation of Advanced Packaging Technology: CoWoS

(Photo credit: Amkor)

TSMC is set to conduct an investor meeting on the 19th, with Morgan Stanley, UBS, and Bank of America Securities releasing their latest reports ahead of the event. These reports highlight five main areas of interest:

1. Q4 Operational Outlook
2. Future Gross Margin Trends
3. Potential Adjustments to Full-Year Revenue Estimates and Capital Expenditure
4. Economic and Operational Outlook for the Coming Year
5. 2nm Production Plans

Despite market uncertainties surrounding factors such as end-market demand, the Chinese mainland’s economic trajectory, and semiconductor industry cycles, Morgan Stanley Securities anticipates a 10% QoQ increase in TSMC’s Q4 revenue. They attribute this to strong demand for AI GPUs and ASICs, urgent orders from products like smartphone system-on-chips (SoCs) and PC GPUs, as well as sustained demand for Apple’s iPhones. Additionally, the gross margin is expected to benefit from the depreciation of the New Taiwan Dollar, potentially reaching 53%, surpassing the market consensus of 52.2%.

Bank of America Securities similarly projects a 10% QoQ revenue growth for TSMC in Q4, with a gross margin estimate of 52.7%. UBS Securities, on the other hand, has adjusted its Q4 revenue growth forecast from 10% to 7% while maintaining their expectation of a 10% YoY decline in full-year revenue.

In terms of capital expenditures, Morgan Stanley Securities, taking into account factors such as Intel’s 3nm outsourcing and delays in the U.S. factory expansion, estimates that TSMC’s capital expenditures will remain around $28 billion for both this year and the next. UBS Securities, however, believes that due to a slower short-term business recovery, capital expenditures for this year and the next will be adjusted to $31 billion and $30 billion, respectively.

Explore More

• TSMC to Receive One More Year of Exemption Amid U.S. Chip Export Ban to China
• TSMC’s 2nm Fab in Kaohsiung Prepares for N2P Mass Production

(Photo credit: TSMC)

As AI demand continues to surge, TSMC (Taiwan Semiconductor Manufacturing Company) has initiated an extensive expansion plan for its CoWoS (Chip-on-Wafer-on-Substrate) production. Within the industry, reports suggest that TSMC, a leading semiconductor foundry, placed a significant wave of orders with Taiwanese equipment manufacturers last week, creating a notable impact.

Additionally, outsourced semiconductor assembly and testing (OSAT) giants, which were originally inquiring about orders, have also significantly increased their orders for advanced packaging. This wave of orders is estimated to be fulfilled between March and April of the upcoming year.

The growth in demand for advanced semiconductor processes due to AI applications necessitates advanced packaging technologies to keep pace. With packaging technologies advancing from 2D and 2.5D to the more advanced 3D IC (Integrated Circuit) configurations, the number of IC stacking layers is increasing, leading to a greater demand for advanced packaging equipment. Considering the current emphasis on CoWoS technology, the industry estimates that production capacity will reach 12,000 to 14,000 wafers in 2023 and double to over 30,000 wafers in 2024.

According to a report by Taiwan’s Money DJ, information from equipment industry sources reveals that TSMC recommenced orders for CoWoS equipment in April 2023, with a second wave of orders in June. Subsequently, sporadic additional orders were placed, and last week witnessed a new significant wave of orders, surprising many.

An anonymous executive from a Taiwanese equipment company expressed that they initially believed TSMC’s orders for CoWoS equipment had concluded, making the recent wave of orders even more unexpected. Furthermore, the increase in orders for advanced packaging equipment by semiconductor testing and packaging facilities is also seen as encouraging.

Market experts believe that semiconductor testing and packaging facilities and semiconductor foundries have different positions and advantages in the advanced packaging market. Their cooperative relationships outweigh their competition. Major OSAT players like ASE, Amkor, and JCET have long possessed advanced packaging technology and are positioned to become an alternative choice for major foundries due to their technical upgrades and competitive pricing. In other words, top-tier orders from customers will be firmly in TSMC’s grasp, while other opportunities will likely be pursued by SATS companies.

Regarding the supply of CoWoS equipment, suppliers like Scientech have received over 30 orders for wet etching processing equipment, while Grand Process Technology and others have shipped nearly 20 units. Meanwhile, G2C+ Alliance members such as GMM and C Sun have reportedly received over 40 orders from the TSMC’s Longtan factory.

(Photo credit: TSMC)

1. China’s EDA Industry into Fast Development with Efforts of Downstream Industries, Capital and Policies Propel

Within the broader context of China’s push for semiconductor self-sufficiency in recent years, the domestic EDA (Electronic Design Automation) industry in China has undergone remarkable growth. This growth has been spurred by a collaborative effort involving the Chinese government (through policies and investment funds), the expansion of the IC design sector (the growth of IC design scale and investments upstream and downstream), and private offered funds.

EDA companies in China are in rapid growth, and finance companies reached its zenith in 2021, with funding amounts consistently setting new records year after year. In 2022, EDA financing amounted to approximately 8 billion RMB, with companies like Primarius Technologies, Empyrean Technology, and Semitronix making their debut on the stock market. Over the past three years, these companies have sustained a continuous uptrend in their revenues. All in all, with support from various quarters, China’s EDA industry is now on a fast track to development.

2. Point Tools Take Center Stage for Chinese EDA Companies

Nowadays, the supply of EDA tools is largely controlled by Synopsys, Cadence, and Siemens EDA, three major players with deep technical expertise across the entire spectrum of EDA tools. While Empyrean Technology, having entered the arena early, boasts a comprehensive suite of EDA tools for analog circuit design and FPD, the majority of other Chinese EDA firms are strategically focusing on specialized point tools in simulation and verification.

These companies win customer recognition and purchases before broadening their path to other tool categories. Another strategic avenue pursued by Chinese EDA companies is the exploration of innovative opportunities in emerging fields such as AI chips, setting them apart from their larger counterparts.

3. China’s EDA Industry Enters a Phase of Consolidation, Confronting Challenges of Inexperience and Political Risks

Over the past few years, the number of Chinese EDA companies and the scale of funding have surged dramatically. As they experience rapid growth, mergers and acquisitions (M&A) and investments have become indispensable means for Chinese EDA firms to fortify their positions. This trend is becoming increasingly conspicuous, with a total of 20 M&A and investment deals occurring within the Chinese EDA sectors over the past three years, comprising 2 in 2021, 15 in 2022, and 3 in the first half of 2023.

Primarius Technologies (with 9 deals), Empyrean Technology (with 3 deals), and Univesta (with 4 deals, one of which was unsuccessful) are among the firms with comparatively high M&A activity. Beyond M&A and investment, Chinese EDA companies are accelerating their collaborations to achieve complementary advantages, a trend that is expected to continue to gain momentum in the future.

China’s EDA companies do encounter certain challenges during the integration process: (1) They lack prior experience in M&A and must continually learn and experiment. (2) Given the global semiconductor industry’s shifting dynamics, they may encounter obstacles from local governments when pursuing overseas M&A and investments.

As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source：ISSCC 2021)

3D-SIP

System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source：TrendTorce (Left)，ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.

3D-SIC

The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )