According to a report by Taiwan’s Economic Daily, TSMC is aggressively expanding its advanced packaging capacity. Recently, they placed an additional 30% order for equipment with manufacturers, leading to a doubling of order volumes for companies in the interposer supply chain, such as UMC and ASE Group. Moreover, there are rumors of price increases on the horizon.

TSMC, responding to the robust production demands from major clients like NVIDIA, AMD, and Amazon, has not only expanded its CoWoS capacity as originally planned but has also added another 30% in new equipment. This move implies that once TSMC’s new advanced packaging capacity comes online next year, it will represent at least a doubling of the current production capacity.

Given the substantial demand for TSMC’s advanced packaging orders, coupled with the necessity of interposer in CoWoS for stacking logic computing ICs and high-bandwidth memory, there is an expectation of significant growth in interposer orders, likely exceeding a twofold increase compared to this year. Notably, semiconductor giants like UMC and ASE Group have already secured significant orders from TSMC for interposer layers and are currently in the mass production and delivery stages.

It is understood that UMC, after venturing into the advanced packaging market in recent years, has introduced packaging solutions applicable to IoT, automotive chips, and more, spanning from wafer bumping and wire bonding packaging to advanced 2.5D, 3DIC, and wafer-level fan-out packaging solutions. The most notable among them is the 2.5D silicon interposer layer solution, which, through collaboration with UMC and other specialized packaging facilities, has proven pivotal in securing major orders in the interposer layer market, particularly from NVIDIA.

Industry sources suggest that UMC has increased prices for super hot run interposer layer orders and initiated capacity expansion plans to meet customer demands, while ASE Group is also contemplating adjustments to its advanced packaging quotations.

(Photo credit: UMC)

According to a report by Taiwan’s Economic Daily, TSMC’s CoWoS advanced packaging capacity is running at full throttle. As they actively expand their production capabilities, there are reports of major customers like NVIDIA increasing their orders for AI chips. Additionally, industry giants like AMD and Amazon have rushed in with urgent orders.

In response to this urgent situation, TSMC is actively seeking equipment suppliers to expand its CoWoS machine procurement. Beyond TSMC’s existing production expansion goals, the company is further increasing its orders for equipment by an additional 30%, highlighting the ongoing fervor in the AI market.

It is reported that TSMC has sought assistance from equipment manufacturers such as Scientech, Allring, Grand Process Technology, E&R Engineering, and GP Group for this endeavor. They plan to complete the delivery and installation of the equipment by the first half of the coming year. The related equipment manufacturers are experiencing a surge in activity.

Industry sources reveal that TSMC’s CoWoS advanced packaging monthly production capacity is currently around 12,000 units. With their previous expansion efforts, they aimed to gradually increase this to 15,000 to 20,000 units per month. Now, with the addition of more equipment, they are looking at the possibility of reaching capacities of over 25,000 units per month, potentially even approaching 30,000 units. This substantial increase in production capacity positions TSMC to handle a significantly larger volume of AI-related orders.

Equipment providers have pointed out that NVIDIA is currently TSMC’s largest customer for CoWoS advanced packaging, accounting for 60% of the production capacity. Recently, in response to robust demand in AI computing, NVIDIA has increased its orders. Additionally, urgent orders from other customers such as AMD, Amazon, and Broadcom have started to pour in.

(Photo credit: TSMC)

According to a report by Taiwan’s Liberty Times, Taiwan’s Ministry of Economic Affairs Investment Commission (MOEAIC) has given its approval for Taiwan Semiconductor Manufacturing Company (TSMC) to increase its investment in its Arizona subsidiary by an additional $4.5 billion, following a previous approval in March of this year for a $3.5 billion capital injection. The MOEAIC stated that this decision is expected to facilitate the continued growth of Taiwan’s semiconductor industry and strengthen the supply chain linkage between Taiwan and the United States.

On the 18th of this month, the MOEAIC approved a total of eight significant investment cases, including six foreign investments, totaling approximately $5.72 billion.

Among these foreign investment cases, TSMC’s injection of $4.5 billion into its Arizona subsidiary aims to provide operational funding for activities related to the manufacturing, sales, testing, and computer-aided design of integrated circuits and other semiconductor devices.

(Photo credit: TSMC)

According to Taiwan’s Media TechNews, Taiwan Semiconductor Manufacturing Company (TSMC) is actively building its 2-nanometer (2nm) fab, with significant investments in the northern, central, and southern regions of Taiwan. These investments include the Baoshan fab in Hsinchu, the Central Taiwan Science Park fab, and the Nanzi fab in Kaohsiung. However, the latest supply chain reports suggest that the construction progress of the Baoshan fab is slowing down, potentially affecting the original production schedule. Industry sources speculate that mass production may be delayed until 2026.

In response to these rumors, TSMC stated that the factory construction is currently progressing according to the planned schedule.

TSMC had originally planned to construct Fab 20 at the Baoshan Phase 2 site, with a plan for four 12-inch wafer fabs (P1~P4). Risk Production was scheduled for the second half of 2024, followed by mass production in 2025. Currently, the latest progress indicates that the Hsinchu Science Park Administration has initiated public works for the expansion of the Baoshan Phase 2 project, including infrastructure like surrounding roads and wastewater facilities, and is concurrently handing over the land for TSMC to begin construction.

However, based on supply chain reports, the Baoshan fab construction project is slowing down due to subdued semiconductor demand and uncertainties customer adoption. As a result, the originally scheduled mass production in the second half of 2025 may likely be delayed until 2026.

As for the Kaohsiung fab, it is concurrently starting its 2nm construction, with equipment installation operations originally scheduled to begin just one month after the Baoshan fab. It remains uncertain whether the slowdown in the Baoshan fab construction will have a synchronous impact on the Kaohsiung fab. As for the Taichung fab, it has received approval from the Taichung City government, but construction is expected to commence next year. Some media reports suggest that the Central Taiwan Science Park fab may potentially advance to produce at 1.4nm or even 1nm semiconductor nodes.

Externally, there is speculation that TSMC’s 2nm process will employ nanosheet Gate-All-Around (GAA) transistor architecture for the first time, while Samsung has already adopted GAA technology at the 3nm node. Whether this can give Samsung a competitive edge over TSMC remains to be seen. However, due to the high technical complexity, introducing GAA technology in the early stages of development may face significant yield issues.

What is GAA, and how does it differ from the past FinFET technology?

Based on transistor structure, electrons enter from the source and move towards the drain, with their passage controlled by a metal gate (depicted in green). However, as chip miniaturization continues and the line width of the metal gate shrinks, typically below 20 nanometers, electrons may leak, causing electrical leakage and short circuits. This led to the invention of FinFET technology.

(Source: Applied Materials)

FinFET technology involves standing the source and drain regions vertically (depicted in gray), increasing the contact area with the metal gate. This provides strict control over electrons, preventing them from leaking. The vertical structure resembles a fish fin, hence the name “FinFET.”

However, as the technology scales below 3 nanometers, continuing to use FinFET processes may encounter physical limitations, leading to electrical leakage. To address this, fins need to be transitioned from vertical to horizontal, increasing the contact area even further. This results in the concept of “Gate-All-Around Field-Effect Transistor” (GAAFET).

Samsung began researching GAA architecture early and collaborated with IBM and GlobalFoundries to publish related papers in 2017. TSMC is also prepared to employ nanosheet transistor technology when moving to the 2nm node. However, due to the technical challenges of GAA, the development and production timeline may be delayed. Combined with reports of delays in 2nm fab construction, mass production is likely to be postponed until 2026.

TSMC N2 Nanosheet Concept Image. (Source: Screenshot from the video)

According to a report by Taiwan’s Media TechNews, Taiwan’s leading semiconductor foundry, TSMC (Taiwan Semiconductor Manufacturing Company), experienced a significant 2.43% decline in its ADR (American Depositary Receipt) on the last trading day of the previous week in the U.S. stock market. This drop was attributed to media reports indicating that TSMC had requested its suppliers to delay equipment deliveries, subsequently affecting the stock prices of related semiconductor equipment companies. Furthermore, Goldman Sachs Securities has reduced its projections for TSMC’s capital expenditure over the next two years.

Goldman Sachs Securities noted that due to the slower-than-expected recovery in end-market demand, they have adjusted their revenue and capital expenditure estimates for TSMC and believe that both TSMC and UMC, another major semiconductor foundry, might delay their capacity expansion schedules. To enhance efficiency, these companies may also allocate equipment resources more effectively, reducing capital expenditures for 2024 and 2025.

Goldman Sachs Securities estimates that TSMC’s capital expenditure for 2023 will remain around $31.6 billion, with no adjustments made. However, due to the uncertainty surrounding demand recovery, TSMC is likely to reduce the pace of equipment procurement for advanced nodes. Instead, some of Taiwan’s equipment may be relocated to overseas production bases in Japan and the United States. Consequently, Goldman Sachs expects TSMC’s capital expenditure for 2024 to decrease from $28 billion to $25 billion, a 21% reduction compared to 2023. As for 2025, the capital expenditure projection has been adjusted from $36 billion to $35 billion.

Additionally, Goldman Sachs Securities has also lowered the utilization rates for TSMC’s 3nm process. Utilization rates for 2023 and 2024 have been adjusted from 40% and 71% to 36% and 65%, respectively, while the 2025 utilization rate is expected to remain unchanged at 78%. The production capacity for the 3nm process in 2024 and 2025 has also been revised from 80,000 and 90,000 wafers per month to 70,000 and 80,000 wafers per month.

(Photo credit: TSMC)