DRAM Spot Market:

The spot market has not changed noticeably from the previous week and still lacks significant demand momentum. Therefore, spot prices of DDR4 and DDR5 chips have maintained a mostly flat to slightly downward trend. Module houses also hold a conservative demand outlook, so they have yet to actively raise the spot prices of their products.

Currently, the overall price trend remains steady due to suppliers’ efforts to limit supply and prop up prices. However, more chips will be released into the spot market in 2Q24. This supply increase will be especially noticeable for DDR5 products, and spot prices, on the whole, will probably weaken as a result. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) fell by 0.05% from US$1.940 last week to US$1.939 this week.

NAND Flash Spot Market:

Despite enervation from end demand, quotations for NAND Flash wafers and other related products have yet to loosen under the stimulation generated by the ongoing increment of contract prices, and prices are still somewhat being supported on the whole. Additionally, provision from suppliers has not expanded significantly, where overall price dynamics are slightly better than that of DRAM spots. 512Gb TLC wafer spots have risen by 8.26% this week, arriving at US$3.840.

As TSMC and Intel slow down their plans for building fabs in the United States, the supply chain, according to a report from Nikkei Asia, is also said to delay in following suit, with semiconductor material suppliers like Topco Scientific, LCY Chemical, and Chang Chun Group among those named.

Per the same report citing statements from several industry sources, the construction of these fabs has been either postponed or significantly scaled back due to soaring costs of construction materials and labor, as well as a shortage of construction workers.

While some delays may be temporary, other fab construction projects are being thoroughly reassessed, with no specific timetable for resuming. Suppliers attribute the delays in fab construction plans to the slower-than-expected progress of Intel and TSMC in setting up their facilities.

The sources cited in the report also revealed that Solvay, a leading supplier of high-purity hydrogen peroxide for semiconductor use based in Belgium, has postponed the construction of its Arizona plant due to cost concerns and fears that Intel and TSMC’s expansion progress may take longer than expected.

Meanwhile, another major manufacturer of high-purity hydrogen peroxide for semiconductors, Taiwan’s Chang Chun Group, has significantly scaled back the construction of its new Arizona plant due to costs that have exceeded expectations by several times.

Regarding this issue, Chang Chun Group reportedly opted not to provide comments, while Solvay mentioned they are currently investigating the matter.

Topco Scientific has reportedly pointed out that it has acquired land in Arizona, USA. However, the company is currently adjusting its investment schedule for warehouse logistics in Arizona. This adjustment aligns with the progress and demand of its customers in setting up factories, as well as the local infrastructure planning, which includes water and power supply and road construction.

Per the report citing sources, TSMC originally planned to begin mass production at its Arizona plant in 2024. However, this timeline has now been postponed to 2025. Initial expectations for the second fab’s schedule were set for 2026, but it is now likely to be pushed back to 2027-2028

As per a previous report from TechNews, despite the United States outperforms Taiwan in various aspects for foundry construction, the primary obstacle is regulatory issues.

Due to the unique federal structure of the United States, foundry construction must comply with federal, state, and local regulations, resulting in an exceptionally complex regulatory process. Additionally, environmental policies pose obstacles to foundry construction, particularly due to stringent requirements for environmental protection

The report suggests that to enhance the United States’ competitiveness in the global semiconductor industry, the government needs to streamline regulatory processes, eliminate redundant regulations, and establish expedited pathways to accelerate semiconductor industry construction projects.

Additionally, there should be an acceleration of environmental review processes and investment in the development of alternative materials to ensure sustainable semiconductor material supplies.

With the continued growth in global semiconductor demand, the construction speed and efficiency of US semiconductor fabs will directly impact its position in the global market.

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• [News] TSMC’s 4nm Process Powers NVIDIA’s Blackwell Architecture GPU, AI Performance Surpasses Previous Generations by Multiples
• [News] Opening of TSMC Kumamoto Plant Nears, Yet Delay in Arizona Plant – Why is US Semiconductor Fab Construction Lagging Globally?

(Photo credit: TSMC)

Driven by the AI chip wave, “advanced packaging” emerges as the hottest technology in the semiconductor industry. Its significance extends beyond computational power demands, as the escalating cost of semiconductor processes and the limits of Moore’s Law make the “integration capability” of advanced packaging a crucial weapon for industry players to break through.

According to a report from TechNews, TSMC, Intel, and Samsung have all been deeply involved in advanced packaging for many years and have already introduced corresponding solutions. However, these semiconductor giants are not only focused on this aspect.

In addition to their own technologies, they are actively fostering supply chains, setting standards, and building ecosystems. By accelerating the development of advanced packaging technology, they are also laying the groundwork for their future influence.

Intel, for instance, has chosen to start with standardization by proposing the Universal Chiplet Interconnect Express (UCIe) alliance. Through open specifications and standardized connections, the protocol directly adopts mature standards like PCI Express (PCIe) and the recently developed Compute Express Link (CXL).

The reason for starting with chiplet technology is that in recent years, more and more semiconductor companies have discovered that designing chips using Chiplet architecture and integrating them through advanced packaging technology is more cost-effective than traditional System-on-Chip (SoC) approaches.

Therefore, Intel’s focus on connecting chiplets through standards like UCIe is aimed at providing a standardized interface stack for complete chiplet integration. UCIe supports 2D, 2.5D, and bridge packaging, with future development expected to include support for 3D packaging as well.

Intel’s Packaging Test Technology Development Department’s Senior Chief Engineer, Zhiguo Qian, directly involved in the UCIe Alliance, emphasizes that advanced packaging has become a crucial aspect of semiconductor development, particularly in ensuring the continuation of Moore’s Law.

Qian further points out that when considering the impact of the UCIe standard on the advanced packaging industry, it indeed establishes a standard for interconnecting chiplets within SoCs. This was the original intent behind Intel’s promotion of the UCIe standard alliance.

Currently, advanced packaging is mostly divided into different structures like 2.5D and 3D, and some even classify it as 2.1D or 2.2D, showcasing diverse structural designs across the industry.

However, within these structures, each company has its own proprietary interface solutions, and some even offer multiple solutions. Therefore, to meet customer demands, these standard interconnections must not only be at the forefront of technology but also be compatible with various standards that are open and do not incur any licensing fees.

On the other hand, the UCIe alliance has established various standards, such as the required packaging architectures and interface wiring designs, to achieve the desired performance levels. These standards provide guidelines for customers seeking advanced packaging solutions. By adhering to UCIe standards, customers can anticipate the performance of their chips, without the need for trial and error(in the IC designing stage).

Source: Intel

Currently, companies participating in the UCIe alliance include Qualcomm, AMD, Arm, NVIDIA, TSMC, ASE Group, Winbond Electronics, and Applied Materials, among others, along with semiconductor giants like Samsung. Additionally, Google Cloud, Microsoft, and Meta are members, alongside over 120 other companies.

• TSMC Propels 3D Fabric Alliance

TSMC is also focused on ecosystem development, as evidenced by its announcement of the 3DFabric Alliance within the Open Innovation Platform (OIP) during the 2022 Open Innovation Platform Ecosystem Forum.

In fact, the 3DFabric Alliance is built upon TSMC’s 3DFabric technology introduced in 2020. This technology encompasses a comprehensive solution ranging from advanced processes to silicon stacking and advanced packaging technologies such as CoWoS and InFO.

With an established customer base for its 3DFabric technology, TSMC expanded it into an alliance in 2022. The goal is to assist customers in achieving rapid implementation of chip and system-level innovations while strengthening TSMC’s influence in advanced packaging.

The 3DFabric Alliance marks TSMC’s sixth open innovation platform alliance and is the semiconductor industry’s first alliance aimed at accelerating innovation and enhancing the 3D Integrated Circuit (3D IC) ecosystem in collaboration with partners.

This alliance includes companies in electronic design automation (EDA), silicon intellectual property (IP), design center alliances (DCA)/value chain alliances (VCA), memory, outsourced packaging testing (OSAT), and substrate and testing. Members include Ansys, Cadence, Siemens, ARM, Micron, Samsung, SK Hynix, Amkor, ASE, Advantest, and more.

Source: TSMC

In addition to establishing the alliance, TSMC also introduced the 3Dblox standard during the alliance’s inception. This standard integrates the design ecosystem with validated EDA tools and processes to support 3DFabric technology.

The purpose of this standard is to break the complexity of 3D IC design caused by each EDA supplier using its preferred language. Through the modular 3Dblox standard, key physical stacking and logic connection information in 3D IC design are standardized in a single format, simplifying input and significantly enhancing interoperability among different tools in 3D IC design.

From Intel’s UCIe standard to TSMC’s 3DFabric alliance and 3Dblox standard, it’s evident that in the era of advanced packaging, the key to solidifying the positions and market shares of semiconductor giants lies not only in their individual technological breakthroughs but also in their ability to coordinate and integrate the upstream and downstream industries.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: TSMC)

The Ministry of Energy in Bulgaria has launched 2 separate calls to build new renewable energy capacity and energy storage facilities in the country with more than BGN 535 million (roughly USD 298 million) budget.

The BG-RRP-4.032 tender will support new solar and/or wind power projects with co-located energy storage facilities. A budget of BGN 107.57 million (roughly USD 60 million) has been allocated to aid the construction of at least 200 MW wind and solar capacity along with 100 MW of storage. Projects can have an installed capacity of 200 kW to 2 MW.

The maximum grant available for a single project will cover up to 50% of the eligible costs but it cannot exceed BGN 1.08 million (roughly USD 0.60 million) for 1 MW of installed energy storage capacity.

The other procurement call BG-RRP-4.033 will also support new solar and/or wind energy projects with co-located storage facilities with an installed capacity of more than 200 kW. The total budget for this round is BGN 427.5 million (roughly USD 238 million) to aid the development of a minimum 940 MW renewable energy and 200 MW storage capacity.

Eligible applicants for both these tenders can come from all sectors of the economy, barring those from agriculture, forestry and fisheries.

The tenders have been issued under the country’s National Recovery and Resilience Plan through which it targets to install 1.425 GW new renewable energy and 350 MW energy storage capacity to the national grid.

Launched on March 14, 2024, the last date for bid submission for these tenders is June 12, 2024.

The launch of these tenders follows a consultation round opened by the ministry in October 2023 for 520 MW wind and solar energy along with 150 MW storage capacity.

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• [News] Bulgarian SUNOTEC Signed a Contract with Huawei to Promote the Application of Battery Energy Storage Technology in Europe

(Photo credit: Taiwan Business TOPICS)

The semiconductor industry enters the era of integration. Various foundries are focusing on advanced packaging technologies, but the terminology surrounding advanced packaging can be daunting. This article aims to explain these terms in the simplest way possible.

According to a report from TechNews, currently, there are two main trends in advanced packaging: heterogeneous integration and chiplets.

In fact, the concept of “heterogeneous integration” has been developing for many years and is not exclusive to advanced packaging. It is not only used for the integration of heterogeneous chiplets but also for integrating other non-chip active/passive components into a single package, which is the technology commonly used in traditional Outsourced Semiconductor Assembly and Test Services(OSATs).

• Heterogeneous Integration = Big Building Blocks? Advanced Packaging = Small Building Blocks? 

In the simplest terms, “heterogeneous integration” can be likened to building with large building blocks, while “advanced packaging” is akin to assembling with small building blocks. Some manufacturers, like traditional Outsourced Semiconductor Assembly and Test Services(OSATs), excel in stacking large blocks, such as logic circuits, radio frequency circuits, MEMS (Micro-Electro-Mechanical Systems), or sensors, onto a IC substrate. The stacking of these different large blocks represents the concept of heterogeneous integration.

On the other hand, some blocks are too small to stack effectively, requiring assistance from advanced packaging, typically provided by semiconductor foundries.

Advanced packaging also encompasses 2.5D packaging and 3D packaging. Using the metaphor of building blocks, the former involves horizontally stacking small building blocks on a interposer, while the latter involves vertically stacking small building blocks with interconnection facilitated through Through-Silicon Vias (TSVs), which are ultra-small building blocks.

It’s important to emphasize that stacking blocks is a conceptual representation, and the distinction between large and small blocks is relative. The analogy above refers to heterogeneous integration in traditional packaging, and heterogeneous integration in advanced packaging follows a similar concept, but with even smaller building blocks.

• SoC / SiP / Heterogeneous Integration / Chiplet

With this concept in mind, let’s discuss the applications of heterogeneous integration in advanced packaging:

Among the various packaging types, SoC (System On Chip) involves integrating different chips such as processors and memory, with different functions, redesigned and fabricated using the “same process,” integrated onto a single chip, resulting in a final product with only one chip.

On the other hand, SiP (System in Package) involves connecting multiple chips with “different processes” through “heterogeneous integration” technology, integrated within the same packaging module. Therefore, the final product will be a system with many chips on it, resembling the stacking of different-sized building blocks mentioned earlier.

Therefore, heterogeneous integration refers to integrating different and separately manufactured components (heterogeneous) into higher-level assemblies. These components include blocks of different sizes, such as MEMS devices, passive components, logic chips, and more.

However, at a certain point, for the sake of process development, researchers found that separating components at the right time might facilitate miniaturization. Hence, chiplet was born.

• Is Chiplet the Fusion of Heterogeneous Integration and Advanced Processes?

As demands for ICs become increasingly complex, the size of SoC chips continues to grow. However, cramming too many components onto a limited substrate poses significant challenges, including heightened process complexity and reduced yield.

Hence, the concept of chiplets emerged, advocating for the segmentation of SoC functionalities, such as data storage, computation, signal processing, and data flow management, into smaller individual chips. These chiplets are then integrated through packaging to form a interconnected network.

It’s worth noting that Chiplets are essentially chips, whereas SiP refers to the packaging format. Chiplet architecture enable the reduction of individual chip sizes, simplify circuit design, overcome manufacturing difficulties and yield issues, and offer greater design flexibility.

• Advanced Packaging Technologies in Foundries

Currently, advanced packaging can be broadly categorized into three main types: Wafer-Level Packaging (WLP), 2.5D Packaging, and 3D Packaging. Traditional packaging involves cutting wafers into chips before packaging, while advanced packaging entails packaging the silicon wafer before cutting, requiring subsequent stacking processes in fabs. Therefore, the technology is primarily the responsibility of fabs.

Traditional packaging involves cutting wafers into chips before packaging. Advanced packaging, starting from wafer-level packaging, involves packaging silicon wafers before cutting, and subsequent stacking requires wafer fabrication processes.

Therefore, this article will delve into advanced packaging technologies offered by the three major foundries, with a focus on 2.5D and 3D packaging.

• 2.5DIC / 3DIC Packaging

To further explain using building blocks, the difference between 2.5D and 3DIC packaging lies in the “stacking method.”

In 2.5D packaging, processors, memory, or other chips are stacked horizontally on a silicon interposer using a flip-chip method, with micro bumps connecting different chip’s electronic signals. Through silicon vias (TSVs) in the interposer link to the metal bumps below, then packaged onto the IC substrate, creating tighter interconnections between the chips and the substrate.

In a side view, although the chips are stacked, the essence remains horizontal packaging, with the chips positioned closer together and allowing for smaller chip sizes. Additionally, this is a form of “heterogeneous integration” technology.

3D packaging involves stacking multiple chips (face down) together, directly using through-silicon vias to stack them vertically, linking the electronic signals of different chips above and below, achieving true vertical packaging. Currently, more and more CPUs, GPUs, and memories are starting to adopt 3D packaging technology.

• Hybrid Bonding

Hybrid bonding is one of the die bonding techniques used in advanced chip packaging processes. One of the commercially available technologies in this domain is the “Cu-Cu hybrid bonding.”

In traditional wafer bonding processes, there are interfaces between copper and dielectric materials. With “Cu-Cu hybrid bonding,” metal contacts are embedded within the dielectric material. Through a thermal treatment process, these two materials are bonded together, utilizing the atomic diffusion of copper metal in its solid-state to achieve the bond. This approach addresses challenges encountered in previous flip-chip bonding process.

Compared to flip-chip bonding, hybrid bonding offers several advantages. It allows for achieving ultra-high I/O counts and longer interconnect lengths. By using dielectric material for bonding instead of bottom fillers, the cost of filling is eliminated.

Additionally, hybrid bonding results in minimal thickness compared to chip-on-wafer bonding. This is particularly beneficial for future developments in 3D packaging, where stacking multiple layers of chips is required, as hybrid bonding can significantly reduce the overall thickness.

• Advanced Packaging Moves Towards the Era of Heterogeneous Integration

As the semiconductor industry enters the “post-Moore’s Law era,” the development focus of advanced packaging is gradually shifting from 2D planar structures to 3D stacking and from single-chip designs to multi-chip configurations. Therefore, “heterogeneous integration” will play a crucial role in future advanced packaging.

Currently, prominent companies such as TSMC, Samsung, and Intel are intensifying their research and development efforts and capacity expansions in this field, introducing their innovative packaging solutions.

With ongoing technological advancements and innovations, advanced packaging and heterogeneous integration will play increasingly vital roles in propelling the semiconductor industry towards greater heights, meeting the complex and diverse demands of future electronic devices.

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• [News] The Era of Heterogeneous Integration Approaches: Who Shall Dominate the Advanced Packaging Field?

(Photo credit: Intel)