DRAM Spot Market:

The spot market has shown no demand turnaround this week, so prices there are stagnant. Unlike the situation in the contract market, suppliers are not collectively attempting to moderate the price decline in the spot market due to the lack of a notable rebound in the sales of consumer electronics. Also, high inventories held by module houses are keeping spot prices on a downward trajectory. On the whole, spot prices of DDR4 and DDR5 products continue to show daily drops. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) fell by 0.07% from US$1.461 last week to US$1.460 this week.

NAND Flash Spot Market:

The spot market is seen with a recovery of purchase willingness this week due to the power outage at SK hynix, though TrendForce’s survey confirms that the particular incident has not yielded any impact towards market supply. Low-priced transactions no longer exist among spot prices of NAND Flash after suppliers’ significant drop of production in 2H23, and the declination that lasted for several consecutive weeks is now halted. 512Gb TLC wafer spots have risen by 0.28% this week, arriving at US$1.440.

According to a report by Taiwan’s Commercial Times, JPMorgan’s latest analysis reveals that AI demand will remain robust in the second half of the year. Encouragingly, TSMC’s CoWoS capacity expansion progress is set to exceed expectations, with production capacity projected to reach 28,000 to 30,000 wafers per month by the end of next year.

The trajectory of CoWoS capacity expansion is anticipated to accelerate notably in the latter half of 2024. This trend isn’t limited to TSMC alone; other players outside the TSMC are also actively expanding their CoWoS-like production capabilities to meet the soaring demands of AI applications.

Gokul Hariharan, Head of Research for JPMorgan Taiwan, highlighted that industry surveys indicate strong and unabated AI demand in the latter half of the year. Shortages amounting to 20% to 30% are observed with CoWoS capacity being a key bottleneck and high-bandwidth memory (HBM) also facing supply shortages.

JPMorgan’s estimates indicate that Nvidia will account for 60% of the overall CoWoS demand in 2023. TSMC is expected to produce around 1.8 to 1.9 million sets of H100 chips, followed by significant demand from Broadcom, AWS’ Inferentia chips, and Xilinx. Looking ahead to 2024, TSMC’s continuous capacity expansion is projected to supply Nvidia with approximately 4.1 to 4.2 million sets of H100 chips.

Apart from TSMC’s proactive expansion of CoWoS capacity, Hariharan predicts that other assembly and test facilities are also accelerating their expansion of CoWoS-like capacities.

For instance, UMC is preparing to have a monthly capacity of 5,000 to 6,000 wafers for the interposer layer by the latter half of 2024. Amkor is expected to provide a certain capacity for chip-on-wafer stacking technology, and ASE Group will offer chip-on-substrate bonding capacity. However, these additional capacities might face challenges in ramping up production for the latest products like H100, potentially focusing more on older-generation products like A100 and A800.

(Photo credit: TSMC)

As per a report from Taiwan’s TechNews,” TSMC, Samsung, and Intel have been actively deploying Backside Power Delivery Network (BSPDN) strategies recently, and have announced plans to incorporate BSPDN into their logic chip development roadmap. For instance, Samsung intends to implement BSPDN technology in its 2-nanometer chips, a move unveiled at the VLSI Symposium in Japan.

According to imec, BSPDN aims to alleviate the congestion issues faced by front-end logic chips in later-stage processes. Through Design Technology Co-Optimization (DTCO), more efficient wire designs are achieved in standard cells, aiding in the downsizing of logic standard cell.

In essence, BSPDN can be seen as a refinement of chiplet design. The conventional approach, where logic circuits and memory modules are integrated, is transformed into a configuration with logic functions on the front and power or signal delivery from the back.

While the traditional method of front-side wafer power delivery achieves its purpose, it leads to decreased power density and compromised performance. Nevertheless, the new BSPDN technique has not yet been adopted by foundries.

Samsung claims that, compared to the conventional method, BSPDN reduces area by 14.8%, providing more chip space for additional transistors and improved overall performance. Wire lengths are also cut by 9.2%, reducing resistance, allowing greater current flow, and thereby lowering power consumption while enhancing power transmission efficiency.

In June of this year, Intel also introduced its BSPDN-related innovations under the name ‘PowerVia.’ Team Blue plans to utilize this approach in the Intel 20A process, potentially achieving a chip utilization rate of 90%.

Intel believes PowerVia will address interconnect bottlenecks in silicon architecture, enabling continuous transmission through backside wafer powering. The company anticipates incorporating this novel approach into its Arrow Lake CPUs slated for release in 2024.

Furthermore, according to Taiwan’s supply chain sources, TSMC remains on track to launch its 2-nanometer process in 2025, with mass production expected in the latter half of the year in Hsinchu’s Baoshan. The company’s N2P process, planned for 2026, will feature BSPDN technology.

(Photo credit: Samsung)

According to a report from Taiwan’s Economic Daily, the construction of TSMC’s 2-nanometer fab in the Central Taiwan Science Park (CSTP) is confirmed to be delayed until next year due to land acquisition and construction timelines.

The Taiwan Central Science Park Administration indicated that this project has been delayed by a year and a half, and the operational schedule is now too tight. After receiving approval from the Taichung City government, it still needs to undergo review by the Construction and Planning Agency Ministry of the Interior. It is anticipated that the urban planning announcement by the Taichung City government will be made by the end of the year, a prerequisite for initiating land acquisition procedures. However, meeting this year’s end deadline for land acquisition is now deemed unfeasible.

The Central Science Park Administration was notified by the Taichung City government today that the expansion project for Phase 2 of the CSTP, crucial for TSMC’s 2-nanometer fab, has been scheduled for urban planning review on the 25th of this month.

Due to repeated delays in the urban planning approval process for the CSTP Phase 2 expansion, TSMC recently made the decision to plan for the construction of a 2-nanometer fab in Kaohsiung.

It’s worth noting that the inclusion of the CSTP Phase 2 expansion project in this month’s urban planning review hinges on TSMC’s announcement of its 2-nanometer fab plans in Kaohsiung. The breakthrough came after Taiwan Power Company and Taiwan Water Corporation finally issued assurances that TSMC’s CSTP 2-nanometer fab’s development and operation would not compromise the assurance of power and water supply for Taichung residents, which provided a turning point for the project.

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, Foxconn Group has achieved another triumph in its AI endeavors. The company has secured orders for over 50% of NVIDIA’s HGX GPU base boards, marking the first instance of such an achievement. Adding to this success, Foxconn had previously acquired an order for another NVIDIA DGX GPU base board, solidifying its pivotal role in NVIDIA’s two most crucial AI chip base board orders.

The report highlights that in terms of supply chain source, Foxconn Group stands as the exclusive provider of NVIDIA’s AI chip modules (GPU Modules). As for NVIDIA’s AI motherboards, the suppliers encompass Foxconn, Quanta, Inventec, and Super Micro.

Industry experts analyze that DGX and HGX are currently NVIDIA’s two most essential AI servers, and Foxconn Group has undertaken the monumental task of fulfilling the large order for NVIDIA’s AI chipboards through its subsidiary, Foxconn Industrial Internet (FII). Having previously secured orders for NVIDIA’s DGX base boards, Foxconn Group has now garnered additional orders from FII for the HGX base boards. This expanded supply constitutes more than half of the total, solidifying Foxconn Group’s role as a primary supplier for NVIDIA’s two critical AI chip base board orders.

Furthermore, Foxconn’s involvement doesn’t end with AI chip modules, base boards, and motherboards. The company’s engagement extends downstream to servers and server cabinets, creating a vertically integrated approach that covers the entire AI ecosystem.

(Photo credit: Nvidia)