HBM3e Production Surge Expected to Make Up 35% of Advanced Process Wafer Input by End of 2024, Says TrendForce

TrendForce reports that the three largest DRAM suppliers are increasing wafer input for advanced processes. Following a rise in memory contract prices, companies have boosted their capital investments, with capacity expansion focusing on the second half of this year. It is expected that wafer input for 1alpha nm and above processes will account for approximately 40% of total DRAM wafer input by the end of the year.

HBM production will be prioritized due to its profitability and increasing demand. However, limited yields of around 50–60% and a wafer area 60% larger than DRAM products mean a higher proportion of wafer input is required. Based on the TSV capacity of each company, HBM is expected to account for 35% of advanced process wafer input by the end of this year, with the remaining wafer capacity used for LPDDR5(X) and DDR5 products.

Regarding the latest developments in HBM, TrendForce indicates that HBM3e will become the market mainstream this year, with shipments concentrated in the second half of the year. Currently, SK hynix remains the primary supplier, along with Micron, both utilizing 1beta nm processes and already shipping to NVIDIA. Samsung, using a 1alpha nm process, is expected to complete qualification in the second quarter and begin deliveries mid-year.

Growing demand for DDR5 and LPDDF5(X) to consume more advanced process capacity

In addition to the increasing proportion of HBM demand, the growing content per unit in PCs, servers, and smartphones is driving up the consumption of advanced process capacity each quarter. Servers, in particular, are seeing the highest capacity increase—primarily driven by AI servers with content of 1.75 TB per unit. With the mass production of new platforms like Intel’s Sapphire Rapids and AMD’s Genoa, which require DDR5 memory, DDR5 penetration is expected to exceed 50% by the end of the year.

Meanwhile, as HBM3e shipments are expected to be concentrated in the second half of the year—coinciding with the peak season for memory demand—market demand for DDR5 and LPDDR5(X) is also expected to increase. However, due to financial losses experienced in 2023, manufacturers are being cautious with their capacity expansion plans. Overall, with a higher proportion of wafer input allocated to HBM production, the output of advanced processes will be limited. Consequently, capacity allocation in the second half of the year will be crucial in determining whether supply can meet demand.

Potential DRAM supply shortage due to HBM capacity prioritization 

The increased focus on HBM production could lead to a DRAM supply shortage if there isn’t sufficient expansion of advanced process capacities. Currently, new factory plans are as follows: Samsung expects existing facilities to be fully utilized by the end of 2024. The new P4L plant is slated for completion in 2025, and the Line 15 facility will undergo a process transition from 1Y nm to 1beta nm and above. The capacity of SK hynix’s M16 plant is expected to expand next year, while the M15X plant is also planned for completion in 2025, with mass production starting at the end of next year. Micron’s facility in Taiwan will return to full capacity next year, with future expansions focused on the US. The Boise facility is expected to be completed in 2025, with equipment installations following and mass production planned for 2026.

TrendForce notes that while new factories are scheduled for completion in 2025, the exact timelines for mass production are still uncertain and depend on the profitability of 2024. This reliance on future profits to fund further equipment purchases reinforces the manufacturers’ commitment to maintaining memory price increases this year. Additionally, NVIDIA’s GB200, set to ramp up production in 2025, will feature HBM3e 192/384 GB, potentially doubling HBM output. With HBM4 development on the horizon, if there isn’t significant investment in expanding capacity, the prioritization of HBM could lead to insufficient DRAM supply due to capacity constraints.

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